Question on the scheduling of timer interrupt and FIO interrupt

[wangwudi <wangwudi@hisilicon.com>]

Hi, all
When running some FIO tests on ARM64 server(Kunpeng), frequent NVMe interrupts occupy the
CPU, and the CPU's hardirq load is 100%. The watchdog feed interrupt arch_timer cannot be
responded, triggering the hardlockup.
GIC driver uses GICV3_PRIO_IRQ to set the same priority for arch_timer interrupt and NVMe
interrupt. In GIC spec, "If, on a particular CPU interface, multiple pending interrupts
have the same priority, and have sufficient priority for the interface to signal them to
the PE, it is IMPLEMENTATION DEFINED how the interface selects which interrupt to signal."
Shell we consider setting a higher priority for the arch_timer interrupt to fix this case?

Thanks for your help.
Wangwudi