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The M.2 slot's 3.3V supply rail is GPIO-controlled >> via a TCA9538 I/O expander on I2C4. >> >> The M.2 E key slot hosts a WLAN card connected over PCIe and a Bluetooth >> device connected over UART. Model the connector using the >> pcie-m2-e-connector binding, wiring the PCIe root port and UART5 for >> the respective interfaces. >> >> Reviewed-by: Konrad Dybcio >> Reviewed-by: Manivannan Sadhasivam >> Reviewed-by: Bartosz Golaszewski >> Signed-off-by: Krishna Chaitanya Chundru >> --- >> arch/arm64/boot/dts/qcom/eliza-evk.dtsi | 116 ++++++++++++++++++++++++++++++++ >> 1 file changed, 116 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/eliza-evk.dtsi b/arch/arm64/boot/dts/qcom/eliza-evk.dtsi >> index e47b24f8b827..b35fffb50976 100644 >> --- a/arch/arm64/boot/dts/qcom/eliza-evk.dtsi >> +++ b/arch/arm64/boot/dts/qcom/eliza-evk.dtsi >> @@ -11,6 +11,92 @@ aliases { >> chosen { >> stdout-path = "serial0:115200n8"; >> }; >> + >> + vreg_pcie_m_3p3: regulator-3p3 { >> + compatible = "regulator-fixed"; >> + >> + regulator-name = "vreg_3p3"; >> + regulator-min-microvolt = <3300000>; >> + regulator-max-microvolt = <3300000>; >> + >> + gpio = <&gpio_expander1 6 GPIO_ACTIVE_HIGH>; >> + enable-active-high; >> + }; >> + >> + connector-0 { >> + compatible = "pcie-m2-e-connector"; >> + vpcie3v3-supply = <&vreg_pcie_m_3p3>; >> + w-disable1-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>; >> + w-disable2-gpios = <&pm8550vs_g_gpios 4 GPIO_ACTIVE_HIGH>; > Hmm, Sashiko pointed out the polarity issue here, GPIO_ACTIVE_HIGH. Is it a > mistake? No it is working with active high only, it is how they connected in the HW. - Krishna Chaitanya. > - Mani > >> + >> + pinctrl-0 = <&m2_w_disable1>, <&m2_w_disable2>; >> + pinctrl-names = "default"; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + m2_e_pcie_ep: endpoint@0 { >> + reg = <0>; >> + remote-endpoint = <&pcieport0_ep>; >> + }; >> + }; >> + >> + port@3 { >> + reg = <3>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + m2_e_uart_ep: endpoint@0 { >> + reg = <0>; >> + remote-endpoint = <&uart5_ep>; >> + }; >> + }; >> + }; >> + }; >> +}; >> + >> +&i2c4 { >> + pinctrl-0 = <&qup_i2c4_data_clk>; >> + pinctrl-names = "default"; >> + >> + clock-frequency = <400000>; >> + >> + status = "okay"; >> + >> + gpio_expander1: gpio@3c { >> + compatible = "ti,tca9538"; >> + #gpio-cells = <2>; >> + gpio-controller; >> + reg = <0x3c>; >> + }; >> +}; >> + >> +&pcie0 { >> + status = "okay"; >> +}; >> + >> +&pcie0_phy { >> + vdda-phy-supply = <&vreg_l1k>; >> + vdda-pll-supply = <&vreg_l3k>; >> + >> + status = "okay"; >> +}; >> + >> +&pcie0_port0 { >> + wake-gpios = <&tlmm 114 GPIO_ACTIVE_LOW>; >> + reset-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>; >> + >> + port { >> + pcieport0_ep: endpoint { >> + remote-endpoint = <&m2_e_pcie_ep>; >> + }; >> + }; >> }; >> >> &uart13 { >> @@ -18,3 +104,33 @@ &uart13 { >> >> status = "okay"; >> }; >> + >> +&uart5 { >> + status = "okay"; >> + >> + port { >> + uart5_ep: endpoint { >> + remote-endpoint = <&m2_e_uart_ep>; >> + }; >> + }; >> +}; >> + >> +&pm8550vs_g_gpios { >> + m2_w_disable2: m2-w-disable2-state { >> + pins = "gpio4"; >> + function = "normal"; >> + input-disable; >> + output-enable; >> + bias-disable; >> + power-source = <2>; >> + }; >> +}; >> + >> +&tlmm { >> + m2_w_disable1: m2-w-disable1-state { >> + pins = "gpio35"; >> + function = "gpio"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> +}; >> >> -- >> 2.34.1 >>