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The devicetree only has > a single usb phy, so isn't it sufficient to look up the syscon by > compatible, rather than via phandle + offset? > I didn't design this, I just copied it from starfive,jh7110-pcie-phy.yaml. As that already exists, I'm neither sure we want to change that anymore nor deviate in the pattern here. Jan >> + description: >> + The phandle to System Register Controller syscon node and the PHY connect offset >> + of SYS_SYSCONSAIF__SYSCFG register. Connect PHY to USB controller. >> + >> clocks: >> items: >> - description: PHY 125m >> @@ -47,4 +57,5 @@ examples: >> <&stgcrg 6>; >> clock-names = "125m", "app_125m"; >> #phy-cells = <0>; >> + starfive,sys-syscon = <&sys_syscon 0x18>; >> }; >> -- >> 2.43.0 >> -- Siemens AG, Technology Linux Expert Center