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([2a01:e0a:999:a3a0:2dc5:b516:f0fb:7491]) by smtp.gmail.com with ESMTPSA id d17-20020adfe891000000b003266ece0fe2sm5879650wrm.98.2023.10.02.00.40.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Oct 2023 00:40:05 -0700 (PDT) Message-ID: <8ce6cd97-6d63-4174-a290-40690c81e205@rivosinc.com> Date: Mon, 2 Oct 2023 09:40:04 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/7] Add support to handle misaligned accesses in S-mode To: Conor Dooley Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Atish Patra , Andrew Jones , Evan Green , =?UTF-8?Q?Bj=C3=B6rn_Topel?= , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Ron Minnich , Daniel Maslowski References: <20230926150316.1129648-1-cleger@rivosinc.com> <20230930-patchy-curdle-ef5ee6e1a17c@spud> Content-Language: en-US From: =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= In-Reply-To: <20230930-patchy-curdle-ef5ee6e1a17c@spud> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 30/09/2023 11:23, Conor Dooley wrote: > On Tue, Sep 26, 2023 at 05:03:09PM +0200, Clément Léger wrote: >> Since commit 61cadb9 ("Provide new description of misaligned load/store >> behavior compatible with privileged architecture.") in the RISC-V ISA >> manual, it is stated that misaligned load/store might not be supported. >> However, the RISC-V kernel uABI describes that misaligned accesses are >> supported. In order to support that, this series adds support for S-mode >> handling of misaligned accesses as well support for prctl(PR_UNALIGN). >> >> Handling misaligned access in kernel allows for a finer grain control >> of the misaligned accesses behavior, and thanks to the prctl call, can >> allow disabling misaligned access emulation to generate SIGBUS. User >> space can then optimize its software by removing such access based on >> SIGBUS generation. >> >> Currently, this series is useful for people that uses a SBI that does >> not handled misaligned traps. In a near future, this series will make >> use a SBI extension [1] allowing to request delegation of the >> misaligned load/store traps to the S-mode software. This extension has >> been submitted for review to the riscv tech-prs group. An OpenSBI >> implementation for this spec is available at [2]. >> >> This series can be tested using the spike simulator [3] and an openSBI >> version [4] which allows to always delegate misaligned load/store to >> S-mode. > > Some patches in this series do not build for any configs, some are > broken for clang builds and others are broken for nommu. Please try to> build test this more thoroughly before you submit the next version. Hi Conor, Thanks for the feedback, I'll check that. > > Also, AIUI, this series should be marked RFC since the SBI extension > this relies on has not been frozen. This series does not actually uses the SBI extension but provides a way to detect if misaligned accesses are not handled by hardware nor by the SBI. It has been reported by Ron & Daniel they they have a minimal SBI implementation that does not handle misaligned accesses and that they would like to make use of the PR_SET_UNALIGN feature. This is what this series addresses (and thus does not depend on the mentioned SBI extension). Thanks, Clément > > Cheers, > Conor.