From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751357AbdJBVgt (ORCPT ); Mon, 2 Oct 2017 17:36:49 -0400 Received: from mail.kernel.org ([198.145.29.99]:45582 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750770AbdJBVgs (ORCPT ); Mon, 2 Oct 2017 17:36:48 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 890262188B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dinguyen@kernel.org Subject: Re: [PATCH] reset: socfpga: fix for 64-bit compilation To: p.zabel@pengutronix.de Cc: linux-kernel@vger.kernel.org References: <1506105767-15889-1-git-send-email-dinguyen@kernel.org> From: Dinh Nguyen Message-ID: <8d03d14e-5c31-e01a-bfe6-7ac17112e258@kernel.org> Date: Mon, 2 Oct 2017 16:36:46 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: <1506105767-15889-1-git-send-email-dinguyen@kernel.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Gentle ping? Dinh On 09/22/2017 01:42 PM, Dinh Nguyen wrote: > The SoCFPGA Stratix10 reset controller has 32-bit registers. Thus, we > cannot use BITS_PER_LONG in computing the register and bit offset. Instead, > we should be using the width of the hardware register for the calculation. > > Signed-off-by: Dinh Nguyen > --- > drivers/reset/reset-socfpga.c | 17 ++++++++++------- > 1 file changed, 10 insertions(+), 7 deletions(-) > > diff --git a/drivers/reset/reset-socfpga.c b/drivers/reset/reset-socfpga.c > index c60904f..3907bbc 100644 > --- a/drivers/reset/reset-socfpga.c > +++ b/drivers/reset/reset-socfpga.c > @@ -40,8 +40,9 @@ static int socfpga_reset_assert(struct reset_controller_dev *rcdev, > struct socfpga_reset_data *data = container_of(rcdev, > struct socfpga_reset_data, > rcdev); > - int bank = id / BITS_PER_LONG; > - int offset = id % BITS_PER_LONG; > + int reg_width = sizeof(u32); > + int bank = id / (reg_width * BITS_PER_BYTE); > + int offset = id % (reg_width * BITS_PER_BYTE); > unsigned long flags; > u32 reg; > > @@ -61,8 +62,9 @@ static int socfpga_reset_deassert(struct reset_controller_dev *rcdev, > struct socfpga_reset_data, > rcdev); > > - int bank = id / BITS_PER_LONG; > - int offset = id % BITS_PER_LONG; > + int reg_width = sizeof(u32); > + int bank = id / (reg_width * BITS_PER_BYTE); > + int offset = id % (reg_width * BITS_PER_BYTE); > unsigned long flags; > u32 reg; > > @@ -81,8 +83,9 @@ static int socfpga_reset_status(struct reset_controller_dev *rcdev, > { > struct socfpga_reset_data *data = container_of(rcdev, > struct socfpga_reset_data, rcdev); > - int bank = id / BITS_PER_LONG; > - int offset = id % BITS_PER_LONG; > + int reg_width = sizeof(u32); > + int bank = id / (reg_width * BITS_PER_BYTE); > + int offset = id % (reg_width * BITS_PER_BYTE); > u32 reg; > > reg = readl(data->membase + (bank * BANK_INCREMENT)); > @@ -132,7 +135,7 @@ static int socfpga_reset_probe(struct platform_device *pdev) > spin_lock_init(&data->lock); > > data->rcdev.owner = THIS_MODULE; > - data->rcdev.nr_resets = NR_BANKS * BITS_PER_LONG; > + data->rcdev.nr_resets = NR_BANKS * (sizeof(u32) * BITS_PER_BYTE); > data->rcdev.ops = &socfpga_reset_ops; > data->rcdev.of_node = pdev->dev.of_node; > >