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Mon, 02 Dec 2024 07:37:08 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4B27b7sJ000401 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 2 Dec 2024 07:37:07 GMT Received: from [10.217.217.81] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sun, 1 Dec 2024 23:37:01 -0800 Message-ID: <8d08c539-6abf-4def-890f-e54176f26efc@quicinc.com> Date: Mon, 2 Dec 2024 13:06:58 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 10/11] clk: qcom: videocc-qcs615: Add QCS615 video clock controller driver To: Bryan O'Donoghue , Bjorn Andersson , Michael Turquette , "Stephen Boyd" , Abhishek Sahu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon CC: Ajit Pandey , Imran Shaik , Jagadeesh Kona , , , , , References: <20241108-qcs615-mm-clockcontroller-v3-0-7d3b2d235fdf@quicinc.com> <20241108-qcs615-mm-clockcontroller-v3-10-7d3b2d235fdf@quicinc.com> Content-Language: en-US From: Taniya Das In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: o78Pex3XS_OFdCfr-0bRkYSDMPy3W05E X-Proofpoint-GUID: o78Pex3XS_OFdCfr-0bRkYSDMPy3W05E X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 suspectscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=959 clxscore=1015 adultscore=0 bulkscore=0 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412020066 On 11/9/2024 10:52 PM, Bryan O'Donoghue wrote: > On 08/11/2024 04:09, Taniya Das wrote: >> +static struct gdsc vcodec0_gdsc = { >> +    .gdscr = 0x874, >> +    .en_rest_wait_val = 0x2, >> +    .en_few_wait_val = 0x2, >> +    .clk_dis_wait_val = 0x6, >> +    .pd = { >> +        .name = "vcodec0_gdsc", >> +    }, >> +    .pwrsts = PWRSTS_OFF_ON, >> +    .flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR, >> +}; >> + >> +static struct gdsc venus_gdsc = { >> +    .gdscr = 0x814, >> +    .en_rest_wait_val = 0x2, >> +    .en_few_wait_val = 0x2, >> +    .clk_dis_wait_val = 0x6, >> +    .pd = { >> +        .name = "venus_gdsc", >> +    }, >> +    .pwrsts = PWRSTS_OFF_ON, >> +    .flags = POLL_CFG_GDSCR, >> +}; >> + > > This looks good to me, except; could you please check if venus gdsc > should be the parent of vcodec0. For the video gdscs we generally do not explicitly need to mention the parent GDSC. -- Thanks & Regards, Taniya Das.