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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-64751035b75sm13571646a12.20.2025.12.01.05.20.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 01 Dec 2025 05:20:46 -0800 (PST) Message-ID: <8d0ec7fc-6eb0-4b71-8e0f-3deaf1f489d6@oss.qualcomm.com> Date: Mon, 1 Dec 2025 14:20:44 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 08/11] clk: qcom: dispcc: Add support for display clock controller Kaanapali To: Dmitry Baryshkov , Taniya Das Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Maxime Coquelin , Alexandre Torgue , Vladimir Zapolskiy , Konrad Dybcio , Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org References: <20251125-kaanapali-mmcc-v2-v2-0-fb44e78f300b@oss.qualcomm.com> <20251125-kaanapali-mmcc-v2-v2-8-fb44e78f300b@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMjAxMDEwOSBTYWx0ZWRfXwat4OfpHvZVM fHKwC2UzdrrBUp11DXI72OQcxYF8mJARGZHHdPuxB26Jr63mYkuuR1N0Uy7M0pGYZBRmzzNb/6v W7TzhP17M997L0jW88DkP2hAaQ9EV3c1yMvL1Onj1Yb2PEzgindfMDLsvYdGeAB6Yt4kryNw81L 57ZNthB2wbdZZVMQ5b7XU4KlN1OTuTFja34hi8IFwMWcPmoqmyTLJvv4+K/AFTiGt2tVbHZIivR zNf7451zJPvDTlTi08FisYYDiAuFvmSD8hNFkVLyOjOKTX1pidrB2iSyHeTfjN+JC0wgybMGPXA LSRpG2j8yGl2N3x2Uej2fy80DBS6Y4/62xzujZlU1tMu3ddaL+zSydwJCdjSXpnzuPKsuONE4CB 9ulm8Hu66ngjuGR6aTgeQ/yj7owytA== X-Authority-Analysis: v=2.4 cv=TbabdBQh c=1 sm=1 tr=0 ts=692d9631 cx=c_pps a=N1BjEkVkxJi3uNfLdpvX3g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=wP3pNCr1ah4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=yXmZhl0dwuD8hoocJaoA:9 a=QEXdDO2ut3YA:10 a=crWF4MFLhNY0qMRaF8an:22 X-Proofpoint-ORIG-GUID: oa5xgHDlUlfXGa4jT9WSbthdgRxjoAbY X-Proofpoint-GUID: oa5xgHDlUlfXGa4jT9WSbthdgRxjoAbY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-28_08,2025-11-27_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 lowpriorityscore=0 suspectscore=0 adultscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2512010109 On 11/26/25 1:09 AM, Dmitry Baryshkov wrote: > On Tue, Nov 25, 2025 at 11:15:17PM +0530, Taniya Das wrote: >> Support the clock controller driver for Kaanapali to enable display SW to >> be able to control the clocks. >> >> Signed-off-by: Taniya Das >> --- [...] >> +/* 257.142858 MHz Configuration */ > > This is a bit strange frequency for the boot config. The frequency map lists this odd cookie as the lowest predefined config, perhaps it was pulled from there. More interestingly, the only consumer of this PLL (MDP_CLK_SRC) makes no effort to use the m/n/d registers, instead relying on the PLL to re-clock for its ratesetting with a fixed divider of 3 (and div1 @ XO rate). 257.142858 * 3 = 771.428574 over-drives MDP_CLK_SRC, FWIW. Taniya, we've seen something like this in camera too. Is there a reason the frequency is being set this way? Konrad > >> +static const struct alpha_pll_config disp_cc_pll0_config = { >> + .l = 0xd, >> + .cal_l = 0x48, >> + .alpha = 0x6492, >> + .config_ctl_val = 0x25c400e7, >> + .config_ctl_hi_val = 0x0a8062e0, >> + .config_ctl_hi1_val = 0xf51dea20, >> + .user_ctl_val = 0x00000008, >> + .user_ctl_hi_val = 0x00000002, >> +}; >> + >