From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from fanzine2.igalia.com (fanzine2.igalia.com [213.97.179.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E956E42DA26 for ; Wed, 8 Jul 2026 16:22:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.97.179.56 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783527764; cv=none; b=d9yykZIfDh6YGMqZmiJ7cIB28MuU2gbJkQPaAZrCV7qzuIHlgF1qIUr8s94PPtx7aPHqXV+1ZsSHlAhkUNirVNnu8gwHraZvZ0MBHWJ7GWhBZQVIyCk6lp/kIh+RMUbTq7p2/3ggJb2LfLK4nLfqClT+CUX5QW7/BEzOa3cXLGA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1783527764; c=relaxed/simple; bh=BBqSyLvzctJq9w2GGcbfoPBAopZt0s/C+FmncLfJLMI=; h=Message-ID:Date:MIME-Version:Subject:To:References:From:Cc: In-Reply-To:Content-Type; b=ftUH+1I40zqK3ohocVyud6UYRgNvEbPuZX9dulFJNveCIGb13sdm/JKFLNqzO3v7Unoswlsc8LWUv1DIfV88AHoRJxYlZ9pPmA802GGNBtBa3SmAGVbm5Wut1NyDP2tfRoQoWKuUYOShxUXigu1nXJmh0bCW0az8i3GuQtK1Wqc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=igalia.com; spf=pass smtp.mailfrom=igalia.com; dkim=pass (2048-bit key) header.d=igalia.com header.i=@igalia.com header.b=Qk+aebJP; arc=none smtp.client-ip=213.97.179.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=igalia.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=igalia.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=igalia.com header.i=@igalia.com header.b="Qk+aebJP" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=igalia.com; s=20170329; h=Content-Transfer-Encoding:Content-Type:In-Reply-To:Cc:From: References:To:Subject:MIME-Version:Date:Message-ID:Sender:Reply-To:Content-ID :Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To: Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe:List-Subscribe :List-Post:List-Owner:List-Archive; bh=oIho4lOceahQWqwg/8lgK/WREkp1NIyVJzaL/dtXx2w=; b=Qk+aebJP6/CUkDhtq/NRXoRatI 0Cb7gyap9J7R+qGwyGYk3I0vPxh8yyruXRlf7LInEBTOy9j5Z2SDq/R+G2e3IUh/nVj9amnuS1/kb U/nOQln4Q3LVIgZFAIcRbP4LIuD/Fiqa4F37Z/GeyAguNg/U2No0XJGse+K1OWZ9W4OGaREJBG938 WyBVLTIb683D3MRXVURKSHM+WT8p52rukYiIo06uL4jU+F0omtl3Wl5ezYrO9rCJ+JB8koRLSYtTm iovknmEV2HiaauaIYpI4LG6iwixL4mgDtXhyKHFxt5wCGaaoVHZ2u6PI4RYO0mEPkzRc1dYu4DRlt SBW9R1iA==; Received: from 189-68-33-146.dsl.telesp.net.br ([189.68.33.146] helo=[192.168.15.100]) by fanzine2.igalia.com with esmtpsa (Cipher TLS1.3:ECDHE_X25519__RSA_PSS_RSAE_SHA256__AES_128_GCM:128) (Exim) id 1whV2i-00BoIK-20; Wed, 08 Jul 2026 18:22:36 +0200 Message-ID: <8d1bd8fb-1c35-4944-ab77-4dfc73ae5056@igalia.com> Date: Wed, 8 Jul 2026 13:22:28 -0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 5/5] riscv: vdso: Implement __vdso_futex_robust_try_unlock() To: Nam Cao References: <7e567e288f9ddeb2128f5d7ed83a518945fb50d9.1781876501.git.namcao@linutronix.de> Content-Language: en-US From: =?UTF-8?Q?Andr=C3=A9_Almeida?= Cc: Alexandre Ghiti , Paul Walmsley , linux-kernel@vger.kernel.org, Palmer Dabbelt , linux-riscv@lists.infradead.org, Albert Ou , =?UTF-8?Q?Thomas_Wei=C3=9Fschuh?= , Mathieu Desnoyers , Thomas Gleixner , Peter Zijlstra , Sebastian Andrzej Siewior , kernel-dev@igalia.com In-Reply-To: <7e567e288f9ddeb2128f5d7ed83a518945fb50d9.1781876501.git.namcao@linutronix.de> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi Nam Cao, thanks for your patch! Em 19/06/2026 11:11, Nam Cao escreveu: > This is the RISC-V port for __vdso_futex_robust_try_unlock(). It is based > on the x86's implementation in commit 61cfc8e372d1 ("x86/vdso: Prepare for > robust futex unlock support") and commit a2274cc0091e ("x86/vdso: Implement > __vdso_futex_robust_try_unlock()"). > [...] > > Signed-off-by: Nam Cao > --- How have you tested it? [...] > diff --git a/arch/riscv/include/asm/vdso/futex.h b/arch/riscv/include/asm/vdso/futex.h > new file mode 100644 > index 000000000000..89a8c425994b > --- /dev/null > +++ b/arch/riscv/include/asm/vdso/futex.h > @@ -0,0 +1,9 @@ > +/* SPDX-License-Identifier: GPL-2.0 */ > + I believe this is missing the ifdef header guard #ifndef __ASM_VDSO_FUTEX_H #define __ASM_VDSO_FUTEX_H [...] > +#if defined(CONFIG_RISCV_ISA_ZACAS) && defined(CONFIG_TOOLCHAIN_HAS_ZACAS) > +#define FUTEX_CAS_OVERWRITE_VDSO_CS_RANGE(vdso, fd, idx, xlen, symbol) \ > +{ \ > + if (riscv_has_extension_unlikely(RISCV_ISA_EXT_ZACAS)) { \ > + void *start = symbol(vdso, CONCAT3(futex_list, xlen, _try_unlock_cs_cas_start));\ > + void *end = symbol(vdso, CONCAT3(futex_list, xlen, _try_unlock_cs_cas_end)); \ > + \ > + futex_set_vdso_cs_range(fd, idx, (uintptr_t)start, (uintptr_t)end, xlen == 32); \ > + } \ > +} > +#else > +#define FUTEX_CAS_OVERWRITE_VDSO_CS_RANGE(...) > +#endif > + > +#define FUTEX_SET_VDSO_CS_RANGE(vdso, fd, idx, xlen, symbol) \ > +{ \ > + void *start = symbol(vdso, CONCAT3(futex_list, xlen, _try_unlock_cs_lrsc_start)); \ > + void *end = symbol(vdso, CONCAT3(futex_list, xlen, _try_unlock_cs_lrsc_end)); \ > + \ > + futex_set_vdso_cs_range(fd, idx, (uintptr_t)start, (uintptr_t)end, xlen == 32); \ > + \ > + FUTEX_CAS_OVERWRITE_VDSO_CS_RANGE(vdso, fd, idx, xlen, symbol); \ > + \ So if the build has support for CAS, the function overwrite what it had just set. Why do it even writes it in the first place then, can't this be an if/else? > +} > + Thanks, André