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[91.159.24.186]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5b2be1d8c57sm315085e87.43.2026.07.25.01.36.52 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 25 Jul 2026 01:36:52 -0700 (PDT) Message-ID: <8d20f3ab-696e-40a4-a05a-688779299071@linaro.org> Date: Sat, 25 Jul 2026 11:36:52 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] i2c: qcom-cci: Add missing cci_clk_rate for msm8953 To: Loic Poulain , Robert Foss , Andi Shyti , Wolfram Sang , Dmitry Baryshkov , Luca Weiss Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260721-cci-clk-fix-v1-0-5eae78700da8@oss.qualcomm.com> <20260721-cci-clk-fix-v1-2-5eae78700da8@oss.qualcomm.com> From: Vladimir Zapolskiy In-Reply-To: <20260721-cci-clk-fix-v1-2-5eae78700da8@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi Loic, Luca, On 7/21/26 17:58, Loic Poulain wrote: > The msm8953 CCI data was added after cci_clk_rate was removed from the > driver, so it never got a clock rate entry. The DT assigns 19.2 MHz to > GCC_CAMSS_CCI_CLK and the hw_params values match those of v1/v1.5 which > were also calibrated for 19.2 MHz. > > Fixes: d202341d9b0c ("i2c: qcom-cci: Add msm8953 compatible") > Signed-off-by: Loic Poulain > --- > drivers/i2c/busses/i2c-qcom-cci.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qcom-cci.c > index 19e4719f13b29b2cf60e113565b1b63f19d0e669..5f74edde8558382e63e2c3d0fbe19489f325e8ce 100644 > --- a/drivers/i2c/busses/i2c-qcom-cci.c > +++ b/drivers/i2c/busses/i2c-qcom-cci.c > @@ -783,6 +783,7 @@ static const struct cci_data cci_msm8953_data = { > .max_write_len = 11, > .max_read_len = 12, > }, > + .cci_clk_rate = 19200000, > .params[I2C_MODE_STANDARD] = { > .thigh = 78, > .tlow = 114, > this simple change is wrong, but commit d202341d9b0c ("i2c: qcom-cci: Add msm8953 compatible") causes it, but please note that the commit d202341d9b0c has no explicit issues per se (if proper frequencies are set in dt), but this particular commit 2/3 breaks the whole picture. Let's see, MSM8953 I2C_MODE_STANDARD/I2C_MODE_FAST settings repeat the ones for v1/v1.5 and 19.2MHz supply clock frequency, but I2C_MODE_FAST_PLUS speed setting very close to v2 parameters and assumes 37.MHz supply clock frequency. So, at least one clock rate setting for all modes is invalid in this case. Automatically it means the reverted commit 1/3 in the series does not directly lead to the wanted and well-managed data, and the logic in 3/3 becomes invalid. I would suggest to grasp the statement above carefully, design a bit better solution, meanwhile postpone applying any commits from the series, especially if a breaking change holds a Fixes tag. -- Best wishes, Vladimir