From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932642AbdA0K1e (ORCPT ); Fri, 27 Jan 2017 05:27:34 -0500 Received: from smtpout.microchip.com ([198.175.253.82]:42348 "EHLO email.microchip.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S932533AbdA0K10 (ORCPT ); Fri, 27 Jan 2017 05:27:26 -0500 Subject: Re: [PATCH v3 1/9] mtd:fsl-quadspi:use the property fields of SPI-NOR To: Yunhui Cui , , , , References: <1471505884-33996-1-git-send-email-B56489@freescale.com> CC: Yunhui Cui , , , , From: Cyrille Pitchen Message-ID: <8d47aefc-063e-533e-e988-57d3bd5c25a8@atmel.com> Date: Fri, 27 Jan 2017 11:27:02 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: <1471505884-33996-1-git-send-email-B56489@freescale.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 8bit X-Brightmail-Tracker: =?Windows-1252?Q?H4sIAAAAAAAAC+NgFnrOKsWRWlGSWpSXmKPExsXCxeXDolup0B1h0LXg?= =?Windows-1252?Q?y3EOi49vtzFZHLmwltli4srJzBbfphxktdi1tYXVYtPja6wWl3fNYbPY?= =?Windows-1252?Q?3bSM3WLxwtuMFj9XtDE6cHn8O9zP5LFz1l12j80rtDw2L6n32PhuB5PH?= =?Windows-1252?Q?501yAWxRrJl5SfkVCawZMy7+ZSvYKFHxad49lgbGicJdjJwcQgIrGCUW?= =?Windows-1252?Q?9HmB2MICfhIzb75l7mLk4hAR6GSUeD6jhR2iyEXi2bd1rCAJZoE5jBLH?= =?Windows-1252?Q?lm9hA0mwCRhKvH1wlBXE5hWwkVjY3w4U5+BgEVCV+HnLDMQUFYiQaDic?= =?Windows-1252?Q?DlEhKHFy5hMWEJtTwFWi8WYT2HhmAQOJI4vmsELY8hLNW2czQ6xVk1jY?= =?Windows-1252?Q?sgLMlhAIlLjytQnKdpLYuXwqC4RtJ3F4+kV2CNtBYunvOewwNe1L37BC?= =?Windows-1252?Q?2NoS21/tg7J1JLYd7IfqtZXYM2MiE4TtLvHg0XIo21di1sMGqJooibfz?= =?Windows-1252?Q?TrFMYJScheSFWUjOnoXk7AWMzKsYpZ09/HSDw3RdI5w9DEz1cpMzCnRz?= =?Windows-1252?Q?EzPz9JLzczcxQqI8awfj786IQ4ySHExKorzWh7sihPiS8lMqMxKLM+KL?= =?Windows-1252?Q?SnNSiw8xynBwKEnwOsl3RwgJFqWmp1akZeYA0w1MmomD8xCjBAePkgjv?= =?Windows-1252?Q?OjmgGt7igsTc4sx0iPwpRkkpcV4XkGYBkERGaR5c7yVGUSlh3tkiQDme?= =?Windows-1252?Q?gtSi3MwSiPgtRjGOh0wcj5mEWPLy81KlgE5lAAIDxleM4hyMSsK8viB7?= =?Windows-1252?Q?eDLzSuDWvAK6gAnoAvEfXSAXlCQipKQaGMOKvKbt0PVdcvCswAFtFrtX?= =?Windows-1252?Q?fwVEY/VLl8TMDIro7ko4esk8Pu3lSTMl2x/G4R6y/36u4WxfuWYfY737?= =?Windows-1252?Q?Vr0bxyy+bag5wmA81yrTbr/MndNNpx085p+Yv0VwzX2BvctUd3N5KGQG?= =?Windows-1252?Q?2ibYO34yT9txzGdVz16ujz17gy8clkuZezIvzHN56cVHl5RYijMSDbWY?= =?Windows-1252?Q?i4oTARMI09F6AwAA?= Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Le 18/08/2016 à 09:37, Yunhui Cui a écrit : > We can get the read/write/erase opcode from the spi nor framework > directly. This patch uses the information stored in the SPI-NOR to > remove the hardcode in the fsl_qspi_init_lut(). > > Signed-off-by: Yunhui Cui > Signed-off-by: Yunhui Cui Applied to the spi-nor tree Thanks! > --- > drivers/mtd/spi-nor/fsl-quadspi.c | 40 ++++++++++++--------------------------- > 1 file changed, 12 insertions(+), 28 deletions(-) > > diff --git a/drivers/mtd/spi-nor/fsl-quadspi.c b/drivers/mtd/spi-nor/fsl-quadspi.c > index 5c82e4e..5ad6402 100644 > --- a/drivers/mtd/spi-nor/fsl-quadspi.c > +++ b/drivers/mtd/spi-nor/fsl-quadspi.c > @@ -373,9 +373,13 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > void __iomem *base = q->iobase; > int rxfifo = q->devtype_data->rxfifo; > u32 lut_base; > - u8 cmd, addrlen, dummy; > int i; > > + struct spi_nor *nor = &q->nor[0]; > + u8 addrlen = (nor->addr_width == 3) ? ADDR24BIT : ADDR32BIT; > + u8 read_op = nor->read_opcode; > + u8 read_dm = nor->read_dummy; > + > fsl_qspi_unlock_lut(q); > > /* Clear all the LUT table */ > @@ -385,20 +389,10 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > /* Quad Read */ > lut_base = SEQID_QUAD_READ * 4; > > - if (q->nor_size <= SZ_16M) { > - cmd = SPINOR_OP_READ_1_1_4; > - addrlen = ADDR24BIT; > - dummy = 8; > - } else { > - /* use the 4-byte address */ > - cmd = SPINOR_OP_READ_1_1_4; > - addrlen = ADDR32BIT; > - dummy = 8; > - } > - > - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), > + qspi_writel(q, LUT0(CMD, PAD1, read_op) | LUT1(ADDR, PAD1, addrlen), > base + QUADSPI_LUT(lut_base)); > - qspi_writel(q, LUT0(DUMMY, PAD1, dummy) | LUT1(FSL_READ, PAD4, rxfifo), > + qspi_writel(q, LUT0(DUMMY, PAD1, read_dm) | > + LUT1(FSL_READ, PAD4, rxfifo), > base + QUADSPI_LUT(lut_base + 1)); > > /* Write enable */ > @@ -409,16 +403,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > /* Page Program */ > lut_base = SEQID_PP * 4; > > - if (q->nor_size <= SZ_16M) { > - cmd = SPINOR_OP_PP; > - addrlen = ADDR24BIT; > - } else { > - /* use the 4-byte address */ > - cmd = SPINOR_OP_PP; > - addrlen = ADDR32BIT; > - } > - > - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), > + qspi_writel(q, LUT0(CMD, PAD1, nor->program_opcode) | > + LUT1(ADDR, PAD1, addrlen), > base + QUADSPI_LUT(lut_base)); > qspi_writel(q, LUT0(FSL_WRITE, PAD1, 0), > base + QUADSPI_LUT(lut_base + 1)); > @@ -432,10 +418,8 @@ static void fsl_qspi_init_lut(struct fsl_qspi *q) > /* Erase a sector */ > lut_base = SEQID_SE * 4; > > - cmd = q->nor[0].erase_opcode; > - addrlen = q->nor_size <= SZ_16M ? ADDR24BIT : ADDR32BIT; > - > - qspi_writel(q, LUT0(CMD, PAD1, cmd) | LUT1(ADDR, PAD1, addrlen), > + qspi_writel(q, LUT0(CMD, PAD1, nor->erase_opcode) | > + LUT1(ADDR, PAD1, addrlen), > base + QUADSPI_LUT(lut_base)); > > /* Erase the whole chip */ >