From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-m19731113.qiye.163.com (mail-m19731113.qiye.163.com [220.197.31.113]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BB6CB17B418 for ; Fri, 14 Aug 2026 01:53:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.197.31.113 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786672428; cv=none; b=JnGwzVi+QEWw1OqN1OeofTdHJxL/LRNZnZ7WAxTkQUBpski7hg7QmzbmPlkQPd5QkvTTgfjeJbiOnw2AMT1pi4K8VVKAIa2TAAhDFEIZbKwiGu9RNL9RqHxmB7LpNsH3tM8iB6Fuu0MS0EvbAQNLRn4T6m+5qXTVoUYewRIzjK0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786672428; c=relaxed/simple; bh=+nOfZ1zyrC46CS0PWYZiLhh+odSaE72RFdmS3FdgPh8=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=mfUCv58hcxnQ4Kt28Z0Iy5wRRVdzWrtD0+poJJBzXi4p0CIMNs76Msk9JOgrg04wZfKNAmwB7TVROgqkhrBtgAHjhb0PC69EzPJQI2lhhhZDDBx0ia8NLd2EemmknQY4fb59Zl6libx+0K84tWjHdlt7Q81ieNJLKovmbzOoNPA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com; spf=pass smtp.mailfrom=rock-chips.com; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b=jy6NpMPI; arc=none smtp.client-ip=220.197.31.113 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rock-chips.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=rock-chips.com header.i=@rock-chips.com header.b="jy6NpMPI" Received: from [172.16.12.90] (unknown [61.154.14.86]) by smtp.qiye.163.com (Hmail) with ESMTP id 49ef6fdfd; Fri, 14 Aug 2026 09:18:03 +0800 (GMT+08:00) Message-ID: <8d521014-3202-4f62-ba1a-ebe126506048@rock-chips.com> Date: Fri, 14 Aug 2026 09:18:01 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] drm/rockchip: vop2: Scale the AXI clock to the bandwidth the mode needs To: Igor Paunovic , Sandy Huang , Heiko Stuebner , Andy Yan Cc: Cristian Ciocaltea , Sebastian Reichel , Alexey Charkov , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org References: <20260813094614.9072-1-royalnet026@gmail.com> <20260813100027.349761F000E9@smtp.kernel.org> <20260813101307.10945-1-royalnet026@gmail.com> Content-Language: en-US From: Chaoyi Chen In-Reply-To: <20260813101307.10945-1-royalnet026@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-HM-Tid: 0a9ffdd8f94d03a7kunm270703397b358 X-HM-MType: 1 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWRgWCB1ZQUpXWS1ZQUlXWQ8JGhUIEh9ZQVkZSBpIVh5MSEJCH00eQx4aSlYVFA kWGhdVEwETFhoSFyQUDg9ZV1kYEgtZQVlNSlVKTk9VSk9VQ01ZV1kWGg8SFR0UWUFZT0tIVUpLSU 9PT0hVSktLVUpCS0tZBg++ DKIM-Signature: a=rsa-sha256; b=jy6NpMPIEbDZlGuNoX291gdYX0VQAcedLCzPYKreLEEpWtqzIYmDm0pR0//ONnM54d4pMnpnGBoyvyiHJ5BPbJ13C2dSPm2V1dB7rQI+u5nFnOKVqmuCURDhrQfFdoMoI6oh1VncTFxhFe76lXnVXqMeRS3loQA0rLwFLLGC+6o=; s=default; c=relaxed/relaxed; d=rock-chips.com; v=1; bh=3dtL6bOxO5qHs+QF6jriizna7ttJ8SGK3f5tUylWokY=; h=date:mime-version:subject:message-id:from; Hi Igor, On 8/13/2026 6:13 PM, Igor Paunovic wrote: > The review bot found three things on v2 and all three are right. I am > answering rather than sending a v3 straight away, because the fix for > the two High ones is a single change that touches a file shared by > every Rockchip SoC, and I would rather ask about that than guess. > > Both High findings come from the same shortcut. v2 keeps the > requirement in a global atomic state object, which I still think is the > right container, but it applies the rate from vop2_crtc_atomic_enable() > and _disable() rather than from the commit tail: > > - Out of order commits. Two non-blocking commits on different CRTCs > share only the private object, and nothing orders them, so a commit > that took its snapshot before another CRTC raised the rate can land > after it and lower it again. > > - Multi-CRTC disable. atomic_disable() runs once per CRTC, and the > first one already sees a state in which every participating CRTC is > off, so the rate drops while the others are still scanning out and > waiting for dsp_hold_completion. > > vc4 solves both of these for its core clock, and what I did was take > half of that pattern instead of all of it: > > - vc4_atomic_commit_setup() records a pending commit per channel in > the private state and the next commit waits on it with > drm_crtc_commit_wait(). That is the ordering v2 has no equivalent > of. > > - vc4_atomic_commit_tail() holds max(old, new) for the length of the > commit and only drops to the new rate after > drm_atomic_helper_wait_for_flip_done(). That is exactly the window > the second finding describes. > > Hence the question. Doing the same in rockchip means adding both > .atomic_commit_setup and .atomic_commit_tail to > rockchip_mode_config_helpers in rockchip_drm_fb.c, which today carries > only .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm and is > shared by every SoC this driver supports, VOP as well as VOP2. The > commit tail would be a thin wrapper around the rpm helper with the > clock work on either side of it, and both hooks would do nothing on > anything that is not RK3588. > As you said, placing it in atomic_commit_tail is precisely because atomic_flush is insufficient to handle multiple CRTC cases. So it's okay for me. Let's see if others have any comments. > Is that acceptable, or would you rather this stayed inside vop2 in some > other shape? I am happy to write it either way, but I would rather find > that out before than after. > > The Medium finding needs no discussion: if > drm_atomic_private_obj_init() fails, the jump to err_crtcs does not > undo rockchip_rgb_init(). It is also new in this patch, since before it > nothing after rockchip_rgb_init() could fail, so it is mine and it will > be fixed in the next version whatever shape the rest takes. > > Igor > > -- Best, Chaoyi