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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-65eab9b5a2bsm2628993a12.15.2026.02.23.05.21.04 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 23 Feb 2026 05:21:06 -0800 (PST) Message-ID: <8d658491-bc1c-410a-97f5-bde1a00764b2@oss.qualcomm.com> Date: Mon, 23 Feb 2026 14:21:03 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/3] arm64: dts: qcom: sm8750: Add GPU clock & IOMMU nodes To: Akhil P Oommen , Taniya Das Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio References: <20260220-gpucc_sm8750_v2-v3-0-6c5408564c3c@oss.qualcomm.com> <20260220-gpucc_sm8750_v2-v3-3-6c5408564c3c@oss.qualcomm.com> <7dbc0e99-cffb-403a-be7a-27d1b47712fd@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <7dbc0e99-cffb-403a-be7a-27d1b47712fd@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMjIzMDExNCBTYWx0ZWRfX979vl7xrztne ky4GXfjKv2NuVtOsXPiEOC0QhlUekLId9J6jjhes53zVgg7j5dG3Vws1yGiCys3YJJMTCIvpLl6 zLtiLd4IiYZdceYfQLgq93nE9hPeYG0DXjxGg7Yr26GT0i3N3VjRTG/+UXKvTchxPLQVIG9oQcF kEuYYdc0jfpivvXvfi7trQy44SruCOFLE9YdM6DUSzS/iqg4LSW20H9U3OjJgEBn0QiZuroWi/4 62oK6jwFUokkut/9YQXtV0OZxxsDX5Qo1JInLbBB9nmEPnMDuI/0FBBO0cqey5Ne+WdpRtzyWi7 lsyjUQin7b7YzpZwfGFuuxyEKLHhDR93g60DLeOQ5Akb5tCJDOSnojcDsoBz3FgsnDwfcPH+afs G3VRCztPU/ILOJhPLQ/p4ylJtfZALc1I/p/fkSbo1vm+uusvE1fIt1GYYFR4pdsMdOAKtLRLSue 9xWE3YsGofpubyFvmEg== X-Authority-Analysis: v=2.4 cv=UO/Q3Sfy c=1 sm=1 tr=0 ts=699c5445 cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=HzLeVaNsDn8A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=6F_KMvjuWJjJSnLB6NgA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-GUID: nEnIZSz3MA2nczHCmuffF4OSgzUin_4q X-Proofpoint-ORIG-GUID: nEnIZSz3MA2nczHCmuffF4OSgzUin_4q X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-02-23_02,2026-02-23_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 lowpriorityscore=0 adultscore=0 impostorscore=0 malwarescore=0 priorityscore=1501 bulkscore=0 phishscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2602130000 definitions=main-2602230114 On 2/21/26 7:22 PM, Akhil P Oommen wrote: > On 2/20/2026 11:24 AM, Taniya Das wrote: >> From: Konrad Dybcio >> >> Add the GPU_CC and GX_CC (brand new! as far as we're concerned, this >> is simply a separate block housing the GX GDSC) nodes, required to >> power up the graphics-related hardware. >> >> Make use of it by enabling the associated IOMMU as well. The GPU itself >> needs some more work and will be enabled later. >> >> Signed-off-by: Konrad Dybcio >> Co-developed-by: Taniya Das >> Signed-off-by: Taniya Das >> --- >> arch/arm64/boot/dts/qcom/sm8750.dtsi | 64 ++++++++++++++++++++++++++++++++++++ >> 1 file changed, 64 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi >> index f56b1f889b857a28859910f5c4465c8ce3473b00..0cc931d0bc96e9563ce4e7989ecd4ba50bd424f8 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi >> @@ -4,7 +4,9 @@ >> */ >> >> #include >> +#include >> #include >> +#include >> #include >> #include >> #include >> @@ -3001,6 +3003,30 @@ videocc: clock-controller@aaf0000 { >> #power-domain-cells = <1>; >> }; >> >> + gxclkctl: clock-controller@3d64000 { >> + compatible = "qcom,sm8750-gxclkctl"; >> + reg = <0x0 0x03d64000 0x0 0x6000>; >> + >> + power-domains = <&rpmhpd RPMHPD_GFX>, >> + <&rpmhpd RPMHPD_GMXC>, >> + <&gpucc GPU_CC_CX_GDSC>; >> + >> + #power-domain-cells = <1>; >> + }; >> + >> + gpucc: clock-controller@3d90000 { >> + compatible = "qcom,sm8750-gpucc"; >> + reg = <0x0 0x03d90000 0x0 0x9800>; >> + >> + clocks = <&bi_tcxo_div2>, >> + <&gcc GCC_GPU_GPLL0_CLK_SRC>, >> + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; >> + >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + #power-domain-cells = <1>; > > On Pakala and newer GPUs, we need to scale GMU (which is connected to > the CX GDSC) freq. Is this DT description sufficient to allow scaling of > GMU OPP? No, certainly not. I see that GPU_CC on this one is exclusively powered by VDD_CX, with some MXA backing, so the natural course of action would be to add a RPMHPD_CX power-domains handle here. Then, voting on the CX_GDSC will propagate the performance state to RPMHPD_CX. Taniya, I see there's also some MXA backing. Do we need to scale it, or is "just ON" fine here? Konrad