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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: 9Unuvn11vGeFvgeaTOpn8ILbjQjYv8Yp X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODI2MDE0MSBTYWx0ZWRfX8UYMMJF/rduU 2WY0ubaE03L4ON8Wfe8UKJlRtmWnzRGMnPqgoTmqvyMdKBXPl+EJYD79o14CO2EqZF1/NrJp0Ij VMbw7PN0hVd3fZFIX+wDnNqSHtIO57qclWtLKAX4pKsjVk1E/+i3xJlElavl7BQxF7sp6FcNhQc ycKNR29btBhiOfgy74+KaulW3oAljC6I5rsyI4u8TE79PW4cucO93BeZacYd9ktH2Wi0mh/3ze4 eVVHbrviS1EapbyitCHD7ZoMeBuuQD31AaC5HPr+JBaE+XjAfJjJ/13bkAhW5DJeoE9KocS3Uaj 6eaydXkBBYyUgJAAQOqreqYgiXDodDbXqGynsTz+Rb9plxVkZ8fPDLlpXzSWrtGJ/i/mgchEx+/ fEC7CVYDkPPM6nJsnQliS3KAPXwd2HNR8JZHbohL8nXzZYYUdGsCmk9bmT3Sj4jhTxJE/xTy9MS OzHK4UbNye0ZCBsCbhQ== X-Authority-Analysis: v=2.4 cv=Y77IdBeN c=1 sm=1 tr=0 ts=6a8f1b84 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=hGlz9nroTSpjRt0Kr7HQew==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=DGHQIYP18U1F1bl52OQA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-ORIG-GUID: 9Unuvn11vGeFvgeaTOpn8ILbjQjYv8Yp X-Proofpoint-Spam-Info: AW1haW4tMjYwODI2MDE0MSBTYWx0ZWRfX5PaWcarXJT4j F1OFv6I845DCSX5LxqWVzKa6zLiaVQkIjOTOnfPVkTjxLF9ZKpv2m9lHUa18zMuAGDK4FT6TWPc JBzu5WG4+2CihcEd322QlihXKGETIeM= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-26_05,2026-08-26_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 phishscore=0 spamscore=0 malwarescore=0 adultscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608260141 On 8/25/2026 10:50 PM, Praveen Talari wrote: > Hi Kathiravan, > > On 12-08-2026 14:00, Kathiravan Thirumoorthy wrote: >> On IPQ5424, the I2C controller can operate on both RTL-hardened SEs >> and firmware-based SEs. As documented in commit 506bb2ab0075 >> ("i2c: qcom-geni: Support systems with 32MHz serial engine clock"), >> in IPQ5424 SEs use a 32 MHz source clock. >> >> The existing frequency table does not provide the required SCL timing >> parameters for firmware-based SEs. Add a dedicated frequency table >> using the SCL counter values recommended by the hardware design team >> and select it for firmware-based SEs to achieve the target bus >> frequencies. >> >> Move geni_i2c_clk_map_idx() from geni_i2c_resources_init() to >> geni_i2c_init() to ensure SE_HW_PARAM_2 is accessed only after the >> required clocks have been enabled. >> >> Signed-off-by: Kathiravan Thirumoorthy >> >> --- >>   drivers/i2c/busses/i2c-qcom-geni.c | 25 ++++++++++++++++++------- >>   include/linux/soc/qcom/geni-se.h   |  1 + >>   2 files changed, 19 insertions(+), 7 deletions(-) >> >> diff --git a/drivers/i2c/busses/i2c-qcom-geni.c >> b/drivers/i2c/busses/i2c-qcom-geni.c >> index 00013b41a6f5..15835f10b062 100644 >> --- a/drivers/i2c/busses/i2c-qcom-geni.c >> +++ b/drivers/i2c/busses/i2c-qcom-geni.c >> @@ -187,19 +187,28 @@ static const struct geni_i2c_clk_fld >> geni_i2c_clk_map_19p2mhz[] = { >>   }; >>     /* source_clock = 32 MHz */ >> -static const struct geni_i2c_clk_fld geni_i2c_clk_map_32mhz[] = { >> +static const struct geni_i2c_clk_fld >> geni_i2c_clk_map_32mhz_minicore[] = { >>       { I2C_MAX_STANDARD_MODE_FREQ, 12, 9, 10, 26 }, >>       { I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 19 }, >>       { I2C_MAX_FAST_MODE_PLUS_FREQ, 2, 3, 5, 15 }, >>       {} >>   }; >>   +static const struct geni_i2c_clk_fld >> geni_i2c_clk_map_32mhz_fwcore[] = { >> +    { I2C_MAX_STANDARD_MODE_FREQ, 12, 9, 10, 25 }, >> +    { I2C_MAX_FAST_MODE_FREQ, 4, 3, 9, 18 }, >> +    { I2C_MAX_FAST_MODE_PLUS_FREQ, 1, 6, 15, 29 }, >> +    {} >> +}; >> + >>   static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c) >>   { >>       const struct geni_i2c_clk_fld *itr; >> +    bool is_minicore = FIELD_GET(GEN_USE_MINICORES, >> +                     readl_relaxed(gi2c->se.base + SE_HW_PARAM_2)); >>         if (clk_get_rate(gi2c->se.clk) == 32 * HZ_PER_MHZ) >> -        itr = geni_i2c_clk_map_32mhz; >> +        itr = is_minicore ? geni_i2c_clk_map_32mhz_minicore : >> geni_i2c_clk_map_32mhz_fwcore; > The source selection remains unchanged when using 32 MHz: > writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL); I have to check on this. But in downstream, we didn't change this configuration. > > However, what about the voltage requirements associated with the > higher frequency? There are no such requirements in the IPQ SoC. > > Are they automatically managed by the underlying provider, or is > additional handling needed in the driver? > > Reference of konrad change for CCI I2C driver for 37.5MHz with voltage > requirement. > > https://lore.kernel.org/linux-arm-msm/20250904-topic-cci_updates-v1-4-d38559692703@oss.qualcomm.com/ > > > > Thanks, > > Praveen Talari