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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5d3ecef4c07sm7164140a12.1.2024.12.12.12.10.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Dec 2024 12:10:32 -0800 (PST) Message-ID: <8d854f93-36da-4779-9ab0-381912aef4b4@oss.qualcomm.com> Date: Thu, 12 Dec 2024 21:10:29 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 3/7] drm/msm: adreno: dynamically generate GMU bw table To: Neil Armstrong , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , Dmitry Baryshkov , Marijn Suijten , David Airlie , Simona Vetter , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Akhil P Oommen Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org References: <20241211-topic-sm8x50-gpu-bw-vote-v5-0-6112f9f785ec@linaro.org> <20241211-topic-sm8x50-gpu-bw-vote-v5-3-6112f9f785ec@linaro.org> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20241211-topic-sm8x50-gpu-bw-vote-v5-3-6112f9f785ec@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: Qsnj-PFn9DmU2nhSRIHxneTYEe61WwXp X-Proofpoint-GUID: Qsnj-PFn9DmU2nhSRIHxneTYEe61WwXp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 bulkscore=0 mlxlogscore=999 phishscore=0 adultscore=0 suspectscore=0 spamscore=0 mlxscore=0 impostorscore=0 clxscore=1015 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412120145 On 11.12.2024 9:29 AM, Neil Armstrong wrote: > The Adreno GPU Management Unit (GMU) can also scale the ddr > bandwidth along the frequency and power domain level, but for > now we statically fill the bw_table with values from the > downstream driver. > > Only the first entry is used, which is a disable vote, so we > currently rely on scaling via the linux interconnect paths. > > Let's dynamically generate the bw_table with the vote values > previously calculated from the OPPs. > > Those entries will then be used by the GMU when passing the > appropriate bandwidth level while voting for a gpu frequency. > > Signed-off-by: Neil Armstrong > --- > drivers/gpu/drm/msm/adreno/a6xx_hfi.c | 48 ++++++++++++++++++++++++++++++++++- > 1 file changed, 47 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c > index cb8844ed46b29c4569d05eb7a24f7b27e173190f..995526620d678cd05020315f771213e4a6943bec 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_hfi.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_hfi.c > @@ -6,6 +6,7 @@ > #include > > #include > +#include > > #include "a6xx_gmu.h" > #include "a6xx_gmu.xml.h" > @@ -259,6 +260,48 @@ static int a6xx_hfi_send_perf_table(struct a6xx_gmu *gmu) > NULL, 0); > } > > +static void a6xx_generate_bw_table(const struct a6xx_info *info, struct a6xx_gmu *gmu, > + struct a6xx_hfi_msg_bw_table *msg) > +{ > + unsigned int i, j; > + > + for (i = 0; i < GMU_MAX_BCMS; i++) { > + if (!info->bcms[i].name) > + break; > + msg->ddr_cmds_addrs[i] = cmd_db_read_addr(info->bcms[i].name); > + } > + msg->ddr_cmds_num = i; > + > + for (i = 0; i < gmu->nr_gpu_bws; ++i) > + for (j = 0; j < msg->ddr_cmds_num; j++) > + msg->ddr_cmds_data[i][j] = gmu->gpu_ib_votes[i][j]; > + msg->bw_level_num = gmu->nr_gpu_bws; > + > + /* Compute the wait bitmask with each BCM having the commit bit */ > + msg->ddr_wait_bitmask = 0; > + for (j = 0; j < msg->ddr_cmds_num; j++) > + if (msg->ddr_cmds_data[0][j] & BCM_TCS_CMD_COMMIT_MASK) > + msg->ddr_wait_bitmask |= BIT(j); > + > + /* > + * These are the CX (CNOC) votes - these are used by the GMU > + * The 'CN0' BCM is used on all targets, and votes are basically > + * 'off' and 'on' states with first bit to enable the path. > + */ > + /* The CNoC BCM only needs a simple off/on vote pair on all platforms */ > + msg->cnoc_cmds_addrs[0] = cmd_db_read_addr("CN0"); > + msg->cnoc_cmds_num = 1; > + > + msg->cnoc_cmds_data[0][0] = BCM_TCS_CMD(true, false, 0, 0); > + msg->cnoc_cmds_data[1][0] = BCM_TCS_CMD(true, true, 0, BIT(0)); While it evaluates to the same, I think this is logically 1 (as in, one unit of bus rate). The question of which bit that corresponds to is handled by the macro. Also, a7xx sets values in both x and y parts here, while a6xx only does so in the y part. > + > + /* Compute the wait bitmask with each BCM having the commit bit */ > + msg->cnoc_wait_bitmask = 0; > + for (j = 0; j < msg->cnoc_cmds_num; j++) > + if (msg->cnoc_cmds_data[0][j] & BCM_TCS_CMD_COMMIT_MASK) > + msg->cnoc_wait_bitmask |= BIT(j); This is a very fancy way to say msg->cnoc_wait_bitmask = BIT(0) Konrad