From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753571AbdL1NXR (ORCPT ); Thu, 28 Dec 2017 08:23:17 -0500 Received: from out0-201.mail.aliyun.com ([140.205.0.201]:60398 "EHLO out0-201.mail.aliyun.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751431AbdL1NXQ (ORCPT ); Thu, 28 Dec 2017 08:23:16 -0500 X-Alimail-AntiSpam: AC=PASS;BC=-1|-1;BR=01201311R151e4;CH=green;FP=0|-1|-1|-1|0|-1|-1|-1;HT=e02c03310;MF=qianyue.zj@alibaba-inc.com;NM=1;PH=DS;RN=8;SR=0;TI=SMTPD_---.9wwDuYT_1514467384; Subject: Re: [PATCH v4] x86/microcode/intel: Blacklist the specific BDW-EP for late loading To: Ingo Molnar References: <1514292147-101928-1-git-send-email-qianyue.zj@alibaba-inc.com> <20171228122428.4t2lsutuo3y2i75c@gmail.com> Cc: bp@alien8.de, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, linux-kernel@vger.kernel.org, tony.luck@intel.com From: "Jia Zhang" Message-ID: <8d92a7af-c583-335d-0f2d-c3faa3c29e64@alibaba-inc.com> Date: Thu, 28 Dec 2017 21:23:03 +0800 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.12; rv:45.0) Gecko/20100101 Thunderbird/45.8.0 MIME-Version: 1.0 In-Reply-To: <20171228122428.4t2lsutuo3y2i75c@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org 在 2017/12/28 下午8:24, Ingo Molnar 写道: > > * Jia Zhang wrote: > >> Instead of blacklisting all types of Broadwell processor when running >> a late loading, only BDW-EP (signature 0x406f1, aka family 6, model 79, >> stepping 1) with the microcode version less than 0x0b000021 needs to >> be blacklisted. >> >> The erratum is documented in the the public documentation #334165 (See >> the item BDF90 for details). >> >> Signed-off-by: Jia Zhang >> --- >> arch/x86/kernel/cpu/microcode/intel.c | 12 ++++++++++-- >> 1 file changed, 10 insertions(+), 2 deletions(-) >> >> diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c >> index 8ccdca6..79cad85 100644 >> --- a/arch/x86/kernel/cpu/microcode/intel.c >> +++ b/arch/x86/kernel/cpu/microcode/intel.c >> @@ -910,8 +910,16 @@ static bool is_blacklisted(unsigned int cpu) >> { >> struct cpuinfo_x86 *c = &cpu_data(cpu); >> >> - if (c->x86 == 6 && c->x86_model == INTEL_FAM6_BROADWELL_X) { >> - pr_err_once("late loading on model 79 is disabled.\n"); >> + /* >> + * The Broadwell-EP processor with the microcode version less >> + * then 0x0b000021 may result in system hang when running a late >> + * loading. This behavior is documented in item BDF90, #334165 >> + * (Intel Xeon Processor E7-8800/4800 v4 Product Family). >> + */ >> + if (c->x86 == 6 && c->x86_model == INTEL_FAM6_BROADWELL_X && >> + c->x86_mask == 0x01 && c->microcode < 0x0b000021) { >> + pr_err_once("late loading on cpu (sig 0x406f1) is disabled " >> + "due to erratum causing system hang.\n"); > > Please never break user-readable messages mid-sentence! > > This should be something like: > > pr_err_once("Late loading of the CPU microcode (sig 0x406f1) is disabled due to Intel erratum BDF90 causing system hangs.\n"); > > (note the spelling and readability improvements as well) > > Btw., what does 'sig 0x406f1' refer to? It is so-called processor signature which can be used to identify a model of x86 processor uniquely. It's the return value of cpuid instruction with leaf 1(eax == 1). Jia > > Thanks, > > > Ingo >