From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.2 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41F5BC433F5 for ; Wed, 8 Sep 2021 08:33:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2B56661167 for ; Wed, 8 Sep 2021 08:33:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348266AbhIHIeb (ORCPT ); Wed, 8 Sep 2021 04:34:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34712 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348328AbhIHIeV (ORCPT ); Wed, 8 Sep 2021 04:34:21 -0400 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A5C39C061575; Wed, 8 Sep 2021 01:33:13 -0700 (PDT) Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: eballetbo) with ESMTPSA id 34E781F43198 Subject: Re: [PATCH v10 01/17] dt-bindings: arm: mediatek: mmsys: add power and gce properties To: "jason-jh.lin" , Rob Herring , Matthias Brugger , Chun-Kuang Hu , Philipp Zabel Cc: Maxime Coquelin , David Airlie , Daniel Vetter , Alexandre Torgue , hsinyi@chromium.org, fshao@chromium.org, Yongqiang Niu , nancy.lin@mediatek.com, singo.chang@mediatek.com, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org References: <20210908060312.24007-1-jason-jh.lin@mediatek.com> <20210908060312.24007-2-jason-jh.lin@mediatek.com> From: Enric Balletbo i Serra Message-ID: <8de99666-f9be-320d-96c0-b9e140d3d4b4@collabora.com> Date: Wed, 8 Sep 2021 10:32:37 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.12.0 MIME-Version: 1.0 In-Reply-To: <20210908060312.24007-2-jason-jh.lin@mediatek.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jason, Thank you for your patch. One small comment below. On 8/9/21 8:02, jason-jh.lin wrote: > Power: > 1. Add description for power-domains property. > > GCE: > 1. Add description for mboxes property. > 2. Add description for mediatek,gce-client-reg property. > > Signed-off-by: jason-jh.lin > --- > .../bindings/arm/mediatek/mediatek,mmsys.yaml | 30 ++++++++++++++++++- > 1 file changed, 29 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml > index 2d4ff0ce387b..a2e7bddfed03 100644 > --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml > +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml > @@ -39,6 +39,30 @@ properties: > reg: > maxItems: 1 > > + power-domains: > + description: > + A phandle and PM domain specifier as defined by bindings > + of the power controller specified by phandle. See > + Documentation/devicetree/bindings/power/power-domain.yaml for details. > + > + mboxes: > + description: > + Using mailbox to communicate with GCE, it should have this > + property and list of phandle, mailbox specifiers. See > + Documentation/devicetree/bindings/mailbox/mtk-gce.txt for details. > + $ref: /schemas/types.yaml#/definitions/phandle-array > + > + mediatek,gce-client-reg: > + description: > + The register of client driver can be configured by gce with 4 arguments > + defined in this property, such as phandle of gce, subsys id, > + register offset and size. > + Each subsys id is mapping to a base address of display function blocks > + register which is defined in the gce header > + include/dt-bindings/gce/-gce.h. > + $ref: /schemas/types.yaml#/definitions/phandle-array > + maxItems: 1 > + > "#clock-cells": > const: 1 > > @@ -53,6 +77,10 @@ examples: > - | > mmsys: syscon@14000000 { > compatible = "mediatek,mt8173-mmsys", "syscon"; > - reg = <0x14000000 0x1000>; > + reg = <0 0x14000000 0 0x1000>; Why this change? Thanks, Enric > + power-domains = <&spm MT8173_POWER_DOMAIN_MM>; > #clock-cells = <1>; > + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>, > + <&gce 1 CMDQ_THR_PRIO_HIGHEST>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; > }; >