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([2a01:e0a:59e:9d80:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6dccd3a4c5esm49752486d6.131.2024.12.18.07.11.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 18 Dec 2024 07:11:43 -0800 (PST) Message-ID: <8df1140d-5364-4979-b572-127067b18f90@redhat.com> Date: Wed, 18 Dec 2024 16:11:39 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V2 06/46] arm64/sysreg: Add register fields for HDFGWTR2_EL2 Content-Language: en-US To: Anshuman Khandual , linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, maz@kernel.org Cc: ryan.roberts@arm.com, Oliver Upton , James Morse , Suzuki K Poulose , Catalin Marinas , Will Deacon , Mark Brown References: <20241210055311.780688-1-anshuman.khandual@arm.com> <20241210055311.780688-7-anshuman.khandual@arm.com> From: Eric Auger In-Reply-To: <20241210055311.780688-7-anshuman.khandual@arm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 12/10/24 06:52, Anshuman Khandual wrote: > This adds register fields for HDFGWTR2_EL2 as per the definitions based > on DDI0601 2024-09. > > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Mark Brown > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Reviewed-by: Mark Brown Reviewed-by: Eric Auger Eric > Signed-off-by: Anshuman Khandual > --- > arch/arm64/tools/sysreg | 28 ++++++++++++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg > index a56f7384d0db..1a7d8c03f844 100644 > --- a/arch/arm64/tools/sysreg > +++ b/arch/arm64/tools/sysreg > @@ -2591,6 +2591,34 @@ Field 1 nPMIAR_EL1 > Field 0 nPMECR_EL1 > EndSysreg > > +Sysreg HDFGWTR2_EL2 3 4 3 1 1 > +Res0 63:25 > +Field 24 nPMBMAR_EL1 > +Field 23 nMDSTEPOP_EL1 > +Field 22 nTRBMPAM_EL1 > +Field 21 nPMZR_EL0 > +Field 20 nTRCITECR_EL1 > +Field 19 nPMSDSFR_EL1 > +Res0 18:17 > +Field 16 nSPMSCR_EL1 > +Field 15 nSPMACCESSR_EL1 > +Field 14 nSPMCR_EL0 > +Field 13 nSPMOVS > +Field 12 nSPMINTEN > +Field 11 nSPMCNTEN > +Field 10 nSPMSELR_EL0 > +Field 9 nSPMEVTYPERn_EL0 > +Field 8 nSPMEVCNTRn_EL0 > +Field 7 nPMSSCR_EL1 > +Res0 6 > +Field 5 nMDSELR_EL1 > +Field 4 nPMUACR_EL1 > +Field 3 nPMICFILTR_EL0 > +Field 2 nPMICNTR_EL0 > +Field 1 nPMIAR_EL1 > +Field 0 nPMECR_EL1 > +EndSysreg > + > Sysreg HDFGRTR_EL2 3 4 3 1 4 > Field 63 PMBIDR_EL1 > Field 62 nPMSNEVFR_EL1