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([2607:fea8:fc01:8d8d:5c3d:ce6:f389:cd38]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4945259fa0dsm85842911cf.80.2025.05.14.17.19.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 May 2025 17:19:04 -0700 (PDT) Message-ID: <8e4e3a564b652a1dd402873fbf3d320c8fdc41f8.camel@redhat.com> Subject: Re: [PATCH 3/3] x86: KVM: VMX: preserve host's DEBUGCTLMSR_FREEZE_IN_SMM while in the guest mode From: mlevitsk@redhat.com To: Sean Christopherson Cc: kvm@vger.kernel.org, Thomas Gleixner , Borislav Petkov , Paolo Bonzini , x86@kernel.org, Dave Hansen , Ingo Molnar , linux-kernel@vger.kernel.org, "H. Peter Anvin" Date: Wed, 14 May 2025 20:19:03 -0400 In-Reply-To: References: <20250416002546.3300893-1-mlevitsk@redhat.com> <20250416002546.3300893-4-mlevitsk@redhat.com> <2b1ec570a37992cdfa2edad325e53e0592d696c8.camel@redhat.com> <71af8435d2085b3f969cb3e73cff5bfacd243819.camel@redhat.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.4 (3.52.4-1.fc40) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Thu, 2025-05-08 at 06:35 -0700, Sean Christopherson wrote: > On Wed, May 07, 2025, Sean Christopherson wrote: > > On Thu, May 01, 2025, mlevitsk@redhat.com=C2=A0wrote: > > > Any ideas on how to solve this then? Since currently its the common c= ode that > > > reads the current value of the MSR_IA32_DEBUGCTLMSR and it doesn't le= ave any > > > indication about if it changed I can do either > > >=20 > > > 1. store old value as well, something like 'vcpu->arch.host_debugctl_= old' Ugly IMHO. > > >=20 > > > 2. add DEBUG_CTL to the set of the 'dirty' registers, e.g add new bit= for kvm_register_mark_dirty > > > It looks a bit overkill to me > > >=20 > > > 3. Add new x86 callback for something like .sync_debugctl(). I vote f= or this option. > > >=20 > > > What do you think/prefer? > >=20 > > I was going to say #3 as well, but I think I have a better idea. > >=20 > > DR6 has a similar problem; the guest's value needs to be loaded into ha= rdware, > > but only somewhat rarely, and more importantly, never on a fastpath ree= ntry. > >=20 > > Forced immediate exits also have a similar need: some control logic in = common x86 > > needs instruct kvm_x86_ops.vcpu_run() to do something. > >=20 > > Unless I've misread the DEBUGCTLMSR situation, in all cases, common x86= only needs > > to a single flag to tell vendor code to do something.=C2=A0 The payload= for that action > > is already available. > >=20 > > So rather than add a bunch of kvm_x86_ops hooks that are only called im= mediately > > before kvm_x86_ops.vcpu_run(), expand @req_immediate_exit into a bitmap= of flags > > to communicate what works needs to be done, without having to resort to= a field > > in kvm_vcpu_arch that isn't actually persistent. > >=20 > > The attached patches are relatively lightly tested, but the DR6 tests f= rom the > > recent bug[*] pass, so hopefully they're correct? > >=20 > > The downside with this approach is that it would be difficult to backpo= rt to LTS > > kernels, but given how long this has been a problem, I'm not super conc= erned about > > optimizing for backports. > >=20 > > If they look ok, feel free to include them in the next version.=C2=A0 O= r I can post > > them separately if you want. >=20 > And of course I forgot to attach the patches... There is one problem with this approach though: the common x86 code will st= ill have to decide if to set KVM_RUN_LOAD_DEBUGCTL flag. Checking that DEBUGCTLMSR_FREEZE_IN_SMM bit of 'vcpu->arch.host_debugctl' c= hanged is VMX specific, because AMD doesn't have this bit, and it might even in the future have a d= ifferent bit at that position for different purpose. I can set the KVM_RUN_LOAD_DEBUGCTL when any bit in DEBUGCTL changes instea= d, which should still be rare and then SVM code can ignore the KVM_RUN_LOAD_DEBUGCTL, while VMX code will= reload the VMCS field. Is this OK? Best regards, Maxim Levitsky