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Tue, 02 Jun 2026 07:26:52 -0700 (PDT) Received: from intellaptop.lan ([2607:fea8:fc01:88aa:f1de:f35:7935:804f]) by smtp.gmail.com with ESMTPSA id af79cd13be357-9157f038322sm126685085a.45.2026.06.02.07.26.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 02 Jun 2026 07:26:52 -0700 (PDT) Message-ID: <8e5accc667177fe1d1f955a01a1688fa1b9a9154.camel@redhat.com> Subject: Re: [PATCH 16/28] KVM: nVMX: pass advanced EPT violation vmexit info to guest From: mlevitsk@redhat.com To: Paolo Bonzini , linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: d.riley@proxmox.com, jon@nutanix.com Date: Tue, 02 Jun 2026 10:26:51 -0400 In-Reply-To: <20260505195226.563317-17-pbonzini@redhat.com> References: <20260505195226.563317-1-pbonzini@redhat.com> <20260505195226.563317-17-pbonzini@redhat.com> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.52.4 (3.52.4-2.fc40) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Tue, 2026-05-05 at 21:52 +0200, Paolo Bonzini wrote: > KVM will use advanced vmexit information for EPT violations to > virtualize MBEC.=C2=A0 Pass it to the guest since it is easy and allows > testing nested nested. >=20 > Tested-by: David Riley > Signed-off-by: Paolo Bonzini > --- > =C2=A0arch/x86/include/asm/vmx.h=C2=A0=C2=A0=C2=A0=C2=A0 |=C2=A0 4 ++++ > =C2=A0arch/x86/kvm/mmu/paging_tmpl.h |=C2=A0 2 +- > =C2=A0arch/x86/kvm/vmx/nested.c=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 | 13 ++++++= +++---- > =C2=A03 files changed, 14 insertions(+), 5 deletions(-) >=20 > diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h > index 54aa5be50df9..ed2ded531e55 100644 > --- a/arch/x86/include/asm/vmx.h > +++ b/arch/x86/include/asm/vmx.h > @@ -535,6 +535,7 @@ enum vmcs_field { > =C2=A0#define VMX_EPT_1GB_PAGE_BIT (1ull << 17) > =C2=A0#define VMX_EPT_INVEPT_BIT (1ull << 20) > =C2=A0#define VMX_EPT_AD_BIT =C2=A0=C2=A0=C2=A0 (1ull << 21) > +#define VMX_EPT_ADVANCED_VMEXIT_INFO_BIT (1ull << 22) > =C2=A0#define VMX_EPT_EXTENT_CONTEXT_BIT (1ull << 25) > =C2=A0#define VMX_EPT_EXTENT_GLOBAL_BIT (1ull << 26) > =C2=A0 > @@ -617,6 +618,9 @@ enum vm_entry_failure_code { > =C2=A0 EPT_VIOLATION_PROT_USER_EXEC) > =C2=A0#define EPT_VIOLATION_GVA_IS_VALID BIT(7) > =C2=A0#define EPT_VIOLATION_GVA_TRANSLATED BIT(8) > +#define EPT_VIOLATION_GVA_USER BIT(9) > +#define EPT_VIOLATION_GVA_WRITABLE BIT(10) > +#define EPT_VIOLATION_GVA_NX BIT(11) > =C2=A0 > =C2=A0#define EPT_VIOLATION_RWX_TO_PROT(__epte) (((__epte) & VMX_EPT_RWX_= MASK) << 3) > =C2=A0#define EPT_VIOLATION_USER_EXEC_TO_PROT(__epte) (((__epte) & VMX_EP= T_USER_EXECUTABLE_MASK) >> 4) > diff --git a/arch/x86/kvm/mmu/paging_tmpl.h b/arch/x86/kvm/mmu/paging_tmp= l.h > index 8dd9d510fc34..d4ce55195a7c 100644 > --- a/arch/x86/kvm/mmu/paging_tmpl.h > +++ b/arch/x86/kvm/mmu/paging_tmpl.h > @@ -494,7 +494,7 @@ static int FNAME(walk_addr_generic)(struct guest_walk= er *walker, > =C2=A0 * [2:0] - Derive from the access bits. The exit_qualification migh= t be > =C2=A0 *=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 out of date if i= t is serving an EPT misconfiguration. > =C2=A0 * [5:3] - Calculated by the page walk of the guest EPT page tables > - * [7:8] - Derived from [7:8] of real exit_qualification > + * [7:11] - Derived from [7:11] of real exit_qualification Something that confused me at first, so I am thinking, maybe it is worth mentioning that bits 7:11 are copied not here but in nest= ed_ept_inject_page_fault ? (this is a pre-exiting problem though) > =C2=A0 * > =C2=A0 * The other bits are set to 0. > =C2=A0 */ > diff --git a/arch/x86/kvm/vmx/nested.c b/arch/x86/kvm/vmx/nested.c > index 299d4ca60fb3..46b65475765d 100644 > --- a/arch/x86/kvm/vmx/nested.c > +++ b/arch/x86/kvm/vmx/nested.c > @@ -443,10 +443,14 @@ static void nested_ept_inject_page_fault(struct kvm= _vcpu *vcpu, > =C2=A0 vm_exit_reason =3D EXIT_REASON_EPT_MISCONFIG; > =C2=A0 exit_qualification =3D 0; > =C2=A0 } else { > + u64 mask =3D EPT_VIOLATION_GVA_IS_VALID | > + EPT_VIOLATION_GVA_TRANSLATED; > + if (vmx->nested.msrs.ept_caps & VMX_EPT_ADVANCED_VMEXIT_INFO_BIT) > + mask |=3D EPT_VIOLATION_GVA_USER | > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 EPT_VIOLATION_GVA_WRITABLE | > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 EPT_VIOLATION_GVA_NX; > =C2=A0 exit_qualification =3D fault->exit_qualification; > - exit_qualification |=3D vmx_get_exit_qual(vcpu) & > - =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 (EPT_VIOLATION_GVA_IS_VALID | > - =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 EPT_VIOLATION_GVA_TRANSLATED); > + exit_qualification |=3D vmx_get_exit_qual(vcpu) & mask; > =C2=A0 vm_exit_reason =3D EXIT_REASON_EPT_VIOLATION; > =C2=A0 } > =C2=A0 > @@ -7240,7 +7244,8 @@ static void nested_vmx_setup_secondary_ctls(u32 ept= _caps, > =C2=A0 VMX_EPT_PAGE_WALK_5_BIT | > =C2=A0 VMX_EPTP_WB_BIT | > =C2=A0 VMX_EPT_INVEPT_BIT | > - VMX_EPT_EXECUTE_ONLY_BIT; > + VMX_EPT_EXECUTE_ONLY_BIT | > + VMX_EPT_ADVANCED_VMEXIT_INFO_BIT; > =C2=A0 > =C2=A0 msrs->ept_caps &=3D ept_caps; > =C2=A0 msrs->ept_caps |=3D VMX_EPT_EXTENT_GLOBAL_BIT | Reviewed-by: Maxim Levitsky Best regards, Maxim Levitsky