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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7992b060c4esm14901588b3a.14.2025.10.14.04.17.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 14 Oct 2025 04:17:42 -0700 (PDT) Message-ID: <8e6720e9-6e9b-4530-b2b8-4e27a74665c5@oss.qualcomm.com> Date: Tue, 14 Oct 2025 19:17:34 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/3] arm64: dts: qcom: Add DisplayPort and QMP USB3DP PHY for SM6150 To: Dmitry Baryshkov Cc: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, fange.zhang@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com, li.liu@oss.qualcomm.com References: <20251014-add-displayport-support-to-qcs615-devicetree-v2-0-1209df74d410@oss.qualcomm.com> <20251014-add-displayport-support-to-qcs615-devicetree-v2-2-1209df74d410@oss.qualcomm.com> From: Xiangxu Yin In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=R64O2NRX c=1 sm=1 tr=0 ts=68ee3159 cx=c_pps a=rz3CxIlbcmazkYymdCej/Q==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=Y-oTvv0IyMzSHJg1AAYA:9 a=QEXdDO2ut3YA:10 a=bFCP_H2QrGi7Okbo017w:22 X-Proofpoint-GUID: lqvBqH1fEbo-y7gLd_LuuJDy02E5Ptri X-Proofpoint-ORIG-GUID: lqvBqH1fEbo-y7gLd_LuuJDy02E5Ptri X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDExMDAxOCBTYWx0ZWRfXzhF9WBFLl5qo X6u/GOQyUkgT9ouHuNGKzvvQK+GTsVHkumpCOrHR8nXQHHDZIoQQJTcUw0vzYsVyMKJl1XCWlKA Uvbt901ed8wO0yQ34Y6CFwN70f3A7JWhFwJlpHzZezCWAE79RPF3n3BHRIprjrm/CfWZeTlA1T2 PJ7Iwk1UFU//Cgnrs6dw7Klk5p5/aBH0aV2GmFAtUGM6rl/8k0WFCQul97v9/a9h7I6B5MIAbch eQQsBBh8Zti+GRvmZ5kBbsjr7S2IZu8hQIjiNIXuoggyUieUkOG7rWkpTRYSmtv/aRoZhmjW0s9 VqOMPvfEEaZ9HXMH+D9bLy+MnB+cBVyk9bzZ4vZZ4yvF8mxrpwL+wnWjF6N7DmE19JabEe97rSe +2fiJdAk6HeF9Wb3OOogGGY0//fbFg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-14_02,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 priorityscore=1501 malwarescore=0 adultscore=0 impostorscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510110018 On 10/14/2025 6:18 PM, Dmitry Baryshkov wrote: > On Tue, Oct 14, 2025 at 05:42:11PM +0800, Xiangxu Yin via B4 Relay wrote: >> From: Xiangxu Yin >> >> Introduce DisplayPort controller node and associated QMP USB3-DP PHY >> for SM6150 SoC. Update clock and endpoint connections to enable DP >> integration. >> >> Signed-off-by: Xiangxu Yin >> --- >> arch/arm64/boot/dts/qcom/sm6150.dtsi | 110 ++++++++++++++++++++++++++++++++++- >> 1 file changed, 108 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi b/arch/arm64/boot/dts/qcom/sm6150.dtsi >> index 6128d8c48f9c0807ac488ddac3b2377678e8f8c3..cdf53d74c778c652080b0288278353e20c317379 100644 >> --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi >> @@ -17,6 +17,7 @@ >> #include >> #include >> #include >> +#include >> >> / { >> interrupt-parent = <&intc>; >> @@ -3717,6 +3718,7 @@ port@0 { >> reg = <0>; >> >> dpu_intf0_out: endpoint { >> + remote-endpoint = <&mdss_dp0_in>; >> }; >> }; >> >> @@ -3749,6 +3751,84 @@ opp-307200000 { >> }; >> }; >> >> + mdss_dp0: displayport-controller@ae90000 { >> + compatible = "qcom,sm6150-dp", "qcom,sm8150-dp", "qcom,sm8350-dp"; >> + >> + reg = <0x0 0x0ae90000 0x0 0x200>, >> + <0x0 0x0ae90200 0x0 0x200>, >> + <0x0 0x0ae90400 0x0 0x600>, >> + <0x0 0x0ae90a00 0x0 0x600>, >> + <0x0 0x0ae91000 0x0 0x600>; >> + >> + interrupt-parent = <&mdss>; >> + interrupts = <12>; >> + >> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, >> + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, >> + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, >> + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, >> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>, >> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>; >> + clock-names = "core_iface", >> + "core_aux", >> + "ctrl_link", >> + "ctrl_link_iface", >> + "stream_pixel", >> + "stream_1_pixel"; >> + >> + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, >> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; >> + assigned-clock-parents = <&usb_qmpphy_2 QMP_USB43DP_DP_LINK_CLK>, >> + <&usb_qmpphy_2 QMP_USB43DP_DP_VCO_DIV_CLK>; > Missing PIXEL1_CLK_SRC assignment Ok, will update in next patch. >> + >> + phys = <&usb_qmpphy_2 QMP_USB43DP_DP_PHY>; >> + phy-names = "dp"; >> + >> + operating-points-v2 = <&dp_opp_table>; >> + power-domains = <&rpmhpd RPMHPD_CX>; >> + >> + #sound-dai-cells = <0>; >> + >> + status = "disabled"; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + mdss_dp0_in: endpoint { >> + remote-endpoint = <&dpu_intf0_out>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + mdss_dp0_out: endpoint { > I thought that we need a data-lanes property somewhere here. Ok, will update. >> + }; >> + }; >> + }; >> +