Re: [PATCH v6 2/4] arm64: dts: intel: agilex5: add USB3.1 controller node

["NG, ADRIAN HO YIN" <adrian.ho.yin.ng@altera.com>]

On 9/11/2026 3:21 PM, Krzysztof Kozlowski wrote:
> On Wed, Sep 09, 2026 at 01:04:38AM +0800, Adrian Ng Ho Yin wrote:
>> Add a DTS node for the Synopsys DWC3 USB3.1 controller on the Agilex5 SoC.
>> Place it under a simple-bus with a 40-bit dma-ranges window (#address-cells
>> = 2) to match the USB DMA address width of the interconnect. Enable it in
>> host mode on the SoCDK board.
>>
>> ref and suspend both use AGILEX5_USB31_SUSPEND_CLK because they share the
>> same hardware clock source on this SoC.
>>
>> Signed-off-by: Adrian Ng Ho Yin <adrian.ho.yin.ng@altera.com>
> Same comments apply. From 5 revisions ago!

Hi Krzysztof

You are right! sorry for repeating this across revisions.

v1 feedback was that DTS must not be mixed into a USB-targeted series.
Splitting the USB3 add and USB0 removal into separate commits inside the
same USB series did not address that; both are still SoC/arm64 DTS and
belong outside the USB tree.

I will send v7 as two postings:
1) USB only: dt-bindings + dwc3-generic-plat
2) DTS only: Agilex5 USB3.1 node + SoCDK enable, and USB0 cleanup

Thanks for the patience.

Best regards,
Adrian
>
> Best regards,
> Krzysztof