Re: [PATCH V3 3/3] arm64: dts: nvidia: Add nodes for CMDQV

[Ashish Mhetre <amhetre@nvidia.com>]

On 12/3/2025 4:14 PM, Jon Hunter wrote:
>
>
> On 01/12/2025 16:32, Ashish Mhetre wrote:
>> The Command Queue Virtualization (CMDQV) hardware is part of the
>> SMMUv3 implementation on NVIDIA Tegra SoCs. It assists in
>> virtualizing the command queue for the SMMU.
>>
>> Update SMMU compatible strings to use nvidia,tegra264-smmu to enable
>> CMDQV support. Add device tree nodes for the CMDQV hardware and enable
>> them on the tegra264-p3834 platform where SMMUs are enabled. Each SMMU
>> instance is paired with its corresponding CMDQV instance via the
>> nvidia,cmdqv property.
>>
>> Signed-off-by: Ashish Mhetre <amhetre@nvidia.com>
>> ---
>>   .../arm64/boot/dts/nvidia/tegra264-p3834.dtsi |  8 +++
>>   arch/arm64/boot/dts/nvidia/tegra264.dtsi      | 55 +++++++++++++++++--
>>   2 files changed, 58 insertions(+), 5 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi 
>> b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
>> index 06795c82427a..7e2c3e66c2ab 100644
>> --- a/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
>> +++ b/arch/arm64/boot/dts/nvidia/tegra264-p3834.dtsi
>> @@ -23,8 +23,16 @@ iommu@5000000 {
>>               status = "okay";
>>           };
>>   +        cmdqv@5200000 {
>> +            status = "okay";
>> +        };
>> +
>>           iommu@6000000 {
>>               status = "okay";
>>           };
>> +
>> +        cmdqv@6200000 {
>> +            status = "okay";
>> +        };
>>       };
>>   };
>> diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi 
>> b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
>> index f137565da804..5124715caeb3 100644
>> --- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi
>> +++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi
>> @@ -3361,7 +3361,7 @@ bus@8100000000 {
>>                <0x02 0x00000000 0xd0 0x00000000 0x08 0x80000000>; /* 
>> ECAM, prefetchable memory, I/O */
>>             smmu1: iommu@5000000 {
>> -            compatible = "arm,smmu-v3";
>> +            compatible = "nvidia,tegra264-smmu", "arm,smmu-v3";
>>               reg = <0x00 0x5000000 0x0 0x200000>;
>>               interrupts = <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>,
>>                        <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>;
>> @@ -3370,10 +3370,19 @@ smmu1: iommu@5000000 {
>>                 #iommu-cells = <1>;
>>               dma-coherent;
>> +            nvidia,cmdqv = <&cmdqv1>;
>> +        };
>> +
>> +        cmdqv1: cmdqv@5200000 {
>> +            compatible = "nvidia,tegra264-cmdqv";
>> +            status = "disabled";
>> +
>> +            reg = <0x00 0x5200000 0x0 0x830000>;
>> +            interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>
> Like for other devices, the typical ordering is ...
>
>  compatible = "nvidia,tegra264-cmdqv";
>  reg = <0x00 0x5200000 0x0 0x830000>;
>  interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
>  status = "disabled";
>
> So let's follow the same approach here.
>
> Jon
>

Sure, I'll update the ordering in next version. Thanks.