Re: [PATCH v1 3/3] riscv: dts: starfive: jh7110: Add watchdog node

[Xingyu Wu <xingyu.wu@starfivetech.com>]

On 2022/12/2 18:48, Krzysztof Kozlowski wrote:
> On 02/12/2022 10:39, xingu.wu wrote:
>> From: Xingyu Wu <xingyu.wu@starfivetech.com>
>> 
>> This adds the watchdog node for the Starfive JH7110 SoC.
> 
> Do not use "This commit/patch".
> https://elixir.bootlin.com/linux/v5.17.1/source/Documentation/process/submitting-patches.rst#L95

Will drop 'This'.

> 
>> 
>> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
>> ---
>>  arch/riscv/boot/dts/starfive/jh7110.dtsi | 14 ++++++++++++++
>>  1 file changed, 14 insertions(+)
>> 
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> index c22e8f1d2640..22f5a37d691e 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> @@ -433,5 +433,19 @@ uart5: serial@12020000 {
>>  			reg-shift = <2>;
>>  			status = "disabled";
>>  		};
>> +
>> +		wdog: watchdog@13070000 {
>> +			compatible = "starfive,jh7110-wdt";
>> +			reg = <0x0 0x13070000 0x0 0x10000>;
>> +			interrupts = <68>;
>> +			clocks = <&syscrg JH7110_SYSCLK_WDT_CORE>,
>> +				 <&syscrg JH7110_SYSCLK_WDT_APB>;
>> +			clock-names = "core_clk", "apb_clk";
>> +			resets = <&syscrg JH7110_SYSRST_WDT_APB>,
>> +				 <&syscrg JH7110_SYSRST_WDT_CORE>;
>> +			reset-names = "rst_apb", "rst_core";
>> +			timeout-sec = <15>;
>> +			status = "okay";
> 
> Why? okay is by default
> 

Will drop it.

Best regards,
Xingyu Wu