From: "Fengnan" <changfengnan@bytedance.com>
To: "Luigi Rizzo" <lrizzo@google.com>,
"Christoph Hellwig" <hch@infradead.org>
Cc: "Thomas Gleixner" <tglx@linutronix.de>,
"Marc Zyngier" <maz@kernel.org>,
"Luigi Rizzo" <rizzo.unipi@gmail.com>,
"Paolo Abeni" <pabeni@redhat.com>,
<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>, <netdev@vger.kernel.org>,
<linux-nvme@lists.infradead.org>,
"Guzebing" <guzebing@bytedance.com>,
"Keith Busch" <kbusch@kernel.org>
Subject: Re: [PATCH v5 0/7] Global Software Interrupt Moderation (GSIM)
Date: Wed, 9 Sep 2026 16:52:27 +0800 [thread overview]
Message-ID: <8e816cdc-a714-49d8-943f-677617682352@bytedance.com> (raw)
In-Reply-To: <CAMOZA0Lt99A1H45Hp0Snq4aSEw-Xr_Mh4xA--Cx0Qh_6vsQvOQ@mail.gmail.com>
在 2026/9/9 16:06, Luigi Rizzo 写道:
> On Wed, Sep 9, 2026 at 8:25 AM Christoph Hellwig <hch@infradead.org> wrote:
>> On Sat, Sep 05, 2026 at 10:30:22PM +0200, Thomas Gleixner wrote:
>>>> it appears that GSIM is only effective in scenarios where multi disks at very high
>>>> IOPS; in some cases, there was a noticeable performance regression.
>>>> If there’s something wrong with my configuration, please correct me.
>>> So we have a NVME specific mechanism to tackle the same problem and a
>>> more generic version which is subsystem "independent".
>> I'm not sure they tackle the entirely same problem, although they are
>> very related.
> There is overlap but it is accidental.
> The difference between the two mechanism is the following:
>
> - GSIM addresses hardware limitations (SoCs that create huge PCIe
> backpressure on each MSIx interrupt, eventually reducing the available
> bandwidth too much, regardless of how many CPUs can process interrupts).
> The goal here is to throttle the total MSIx rate, blocking them at
> the source (PCIe device) rather than later in the interrupt controller.
>
> - the NVME mechanism (and NAPI) aim to amortize interrupt processing
> overhead. It does so by recreating some fine grained single-source
> interrupt moderation (something that NICs do in hardware, but NVME
> does not, with 100us being way too coarse for modern SSDs) and an
> adaptive scheme to adjust the delay and decide when to kick in.
That's a great summary.
As for generic solutions, I've tried several approaches before, but none
of them
could achieve the same or close results as NVMe adaptive interrupt polling.
I'm still experimenting with different options.
>
> I think there is a reason for both.
>
> GSIM because it is more general and addresses an issue the others cannot handle
> the subsystem-specific scheme because they can be more efficient
> (eg they can hook into existing helpers like the threaded irq handler,
> call directly the handler without going through the full irq chain,
> use more targeted heuristics to decide when to kick in).
>
> cheers
> luigi
next prev parent reply other threads:[~2026-09-09 8:53 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-19 12:43 Luigi Rizzo
2026-08-19 12:43 ` [PATCH v5 1/7] genirq: Add flags for software interrupt moderation Luigi Rizzo
2026-08-19 12:43 ` [PATCH v5 2/7] genirq: Add GSIM infrastructure Luigi Rizzo
2026-08-19 12:43 ` [PATCH v5 3/7] genirq: Implement core GSIM moderation logic Luigi Rizzo
2026-08-19 12:43 ` [PATCH v5 4/7] genirq: Integrate GSIM into interrupt flow Luigi Rizzo
2026-08-19 12:43 ` [PATCH v5 5/7] genirq: Add GSIM user space configuration (procfs) Luigi Rizzo
2026-08-19 12:43 ` [PATCH v5 6/7] genirq: Adaptive Global Software Interrupt Moderation (GSIM) Luigi Rizzo
2026-08-19 12:43 ` [PATCH v5 7/7] PCI/MSI: re-enable conditional parent mask/unmask with sw moderation Luigi Rizzo
2026-08-20 7:09 ` [PATCH v5 0/7] Global Software Interrupt Moderation (GSIM) Christoph Hellwig
2026-08-20 7:34 ` Luigi Rizzo
2026-08-20 11:46 ` changfengnan
2026-09-05 20:30 ` Thomas Gleixner
2026-09-09 6:25 ` Christoph Hellwig
2026-09-09 8:06 ` Luigi Rizzo
2026-09-09 8:52 ` Fengnan [this message]
2026-10-19 6:44 ` Naman Jain
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