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Thu, 18 Jun 2026 03:22:37 -0700 (PDT) X-Received: by 2002:a05:6a00:760a:b0:845:286d:4675 with SMTP id d2e1a72fcca58-845286d4993mr6180136b3a.10.1781778156810; Thu, 18 Jun 2026 03:22:36 -0700 (PDT) Received: from [10.218.7.34] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8453a8c9770sm2293492b3a.40.2026.06.18.03.22.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 18 Jun 2026 03:22:36 -0700 (PDT) Message-ID: <8ea7d911-8522-43af-8a2f-81ea8479f049@oss.qualcomm.com> Date: Thu, 18 Jun 2026 15:52:29 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/2] thermal: qcom: add support for PMIC5 Gen3 ADC thermal monitoring To: Jonathan Cameron Cc: David Lechner , =?UTF-8?Q?Nuno_S=C3=A1?= , Andy Shevchenko , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , linux-arm-msm@vger.kernel.org, linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Kamal Wadhwa , David Collins , Anjelique Melendez , Neil Armstrong , Stephan Gerhold References: <20260526-gen3_adc_tm-v2-0-702fbac919ac@oss.qualcomm.com> <20260526-gen3_adc_tm-v2-2-702fbac919ac@oss.qualcomm.com> <20260527124220.39ac0b64@jic23-huawei> <27631a0f-b5ba-4181-94f9-aa7726a4054b@oss.qualcomm.com> <20260614200630.2ea04817@jic23-huawei> Content-Language: en-US From: Jishnu Prakash In-Reply-To: <20260614200630.2ea04817@jic23-huawei> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjE4MDA5NiBTYWx0ZWRfX9drEMPrrg2nI GISk/5X7P7L5Y1WVVkfX6jeoEmSAb0swQnH7tyWYx7PK7wJuDeKeKHTt8IrY29mrIhsBQvHFHY2 Cta8+hEQitlif8j0nuoVzE43vrY+vPgRkTM1RBIUQlF+B0A1x9M7zBPb8yk68To3nMc1M6XDMGr 2LZVA8CJZUyAlzSn5+WLZVzIBKHzB+pO5qGonwT7DnT/MsiJMbkU6mmysQtLhiotjyQVKdt3Po0 sqPLkKlht7mC2iZdfAdAOtGJNF5AOCufOKtsrpWZuIXdgaa7+RMwpx2Rb6joZdBIAfEn1vWpmcN OUQeGw2bqczdR+CMGRT2WF5Y9T8M7mr5rAfIIRy2KtQn9uIiLsm82NDbnNZbKRdWoxQ8c1zlq7b C8Ei6hUG3fGZ4kbTch0w7Bi/ct2Y5NHp9SOkrtGhnevb32Si1w40C3LILwMu90HlQSJ4m+TL/4P WdhI90WoEZyel5V/t6g== X-Proofpoint-Spam-Info: AW1haW4tMjYwNjE4MDA5NiBTYWx0ZWRfXwj5vekiEpwW2 xo0qQ+crPKlypiIFWarKwcbOye9OqcKRkKr+R6ufi2nFAAxlGopcAp4wgay66z/HSNvS8MjGrL/ CZgUhY3HtFa0Eb3Xh5xJaNyDH9GY4xc= X-Proofpoint-GUID: 7KxAMK_c7YPi2rmILqj9LpIas_p0ZRHL X-Proofpoint-ORIG-GUID: 7KxAMK_c7YPi2rmILqj9LpIas_p0ZRHL X-Authority-Analysis: v=2.4 cv=WN1PmHsR c=1 sm=1 tr=0 ts=6a33c6ee cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=DDJsQkWvfQMYwb-dyrcA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-18_01,2026-06-17_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 phishscore=0 spamscore=0 priorityscore=1501 adultscore=0 clxscore=1015 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2606180096 Hi Jonathan, On 6/15/2026 12:36 AM, Jonathan Cameron wrote: > >>>> +static irqreturn_t adctm5_gen3_isr_thread(int irq, void *dev_id) >>>> +{ >>>> + struct adc_tm5_gen3_chip *adc_tm5 = dev_id; >>>> + int sdam_index = -1; >>>> + u8 tm_status[2] = { }; >>>> + u8 buf[16] = { }; >>>> + >>>> + for (int i = 0; i < adc_tm5->nchannels; i++) { >>>> + struct adc_tm5_gen3_channel_props *chan_prop = &adc_tm5->chan_props[i]; >>>> + int offset = chan_prop->tm_chan_index; >>>> + bool upper_set, lower_set; >>>> + int ret; >>>> + >>>> + scoped_guard(adc5_gen3, adc_tm5) { >>>> + if (chan_prop->sdam_index != sdam_index) { >>>> + sdam_index = chan_prop->sdam_index; >>>> + ret = adc5_gen3_tm_status_check(adc_tm5, sdam_index, >>>> + tm_status, buf); >>> >>> I think the clear of other sdam interrupt status that sashiko was pointing out >>> is here as somewhat unexpectedly a function called status_check clears as well. >>> >> >> This is the full comment from Sashiko at this point: >> >>> "Does the threaded handler clear statuses across all SDAMs indiscriminately? >> >>> Since this thread loops over all channels and clears the high status on any >>> SDAM with an active event, could it clear a pending event on a different SDAM >>> than the one that triggered the IRQ? >> >>> Because each SDAM has its own independent IRQ line, if the thread clears a >>> pending event on SDAM 1 while servicing SDAM 0, couldn't SDAM 1's subsequent >>> hardirq read a status of 0 and return IRQ_NONE? Could repeated IRQ_NONE >>> returns cause the IRQ subsystem to shut down SDAM 1's interrupt line as a >>> spurious interrupt storm?" >> >> This sequence of events can happen, but it should not be an issue. >> >> It is possible that the threaded handler is called for servicing an >> interrupt on SDAM0, and in the loop there is a violation detected on >> a TM channel on SDAM1, and the SDAM1 TM status is cleared. But in this >> case, this violation would also be handled after we notify the thermal >> framework at the end of the loop, by some threshold update or disablement. >> >> Even if the subsequent hardirq fires for SDAM1 and it returns IRQ_NONE >> as the TM status was cleared, the violation would have been handled >> by some threshold update, so the interrupt would not keep getting >> triggered afterwards for the same threshold's violation. >> >> >> I also checked the conditions from note_interrupt() in kernel/irq/spurious.c, >> for enough repeated IRQ_NONE returns to happen to cause a spurious interrupt >> disablement. >> It looks like there needs to be more than one interrupts returning IRQ_NONE >> within 0.1 second to increment the irqs_unhandled counter once, but there can be >> at most one TM interrupt in one second since we set the time period of >> recurring TM measurement as one second here in the probe: >> >> adc_tm5->chan_props[i].timer = MEAS_INT_1S; >> >> So a spurious interrupt storm is not possible here. > > Whilst sounds valid, it's a convoluted argument given it relies > on us getting spurious interrupts reported, but not enough to trigger > the stuff to stop interrupt storms. The rules around that may change > in future given it's a heuristic to stop us seeing problems on dodgy > hardware. > > Can we just avoid handling interrupts for SDAMs that weren't the one that > triggered this particular interrupt? Thinking more about it, this would be better. I overlooked it before, but we could get the right SDAM from the IRQ number and simplify the logic to handle only that SDAM's channels. I'll make this update in the next patch series. Thanks, JIshnu > > Thanks, > > Jonathan > >