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([2a05:6e02:1041:c10:f14c:b716:c104:4712]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48b82253e5bsm3914595f8f.1.2026.10.02.02.49.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 02 Oct 2026 02:49:51 -0700 (PDT) Message-ID: <8eb0b435-e5d4-4429-a807-24e15b0659fa@oss.qualcomm.com> Date: Fri, 2 Oct 2026 11:49:49 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 0/4] timers: Add support for RZ/N1 SoCs timers To: "Herve Codina (Schneider Electric)" , Wolfram Sang , Daniel Lezcano , Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Geert Uytterhoeven , Magnus Damm Cc: linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Pascal Eberhard , Miquel Raynal , Thomas Petazzoni References: <20261001082225.125956-1-herve.codina@bootlin.com> Content-Language: en-US From: Daniel Lezcano In-Reply-To: <20261001082225.125956-1-herve.codina@bootlin.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: yCbLIbgJr-VPCC5H1NlajJOC0q085kEC X-Proofpoint-Spam-Info: AW1haW4tMjYxMDAyMDAzOSBTYWx0ZWRfX7DF9K8uvULDV S2BCvLWk1z7hSQx/G38zxjrp+tO3uYhVnRkZ5uR0ok8h+PGC8MLxQQSTsLpmoKvM77E5BaGedsL /gqi73Jp6Qr4b8YYVhRLmyU9ZZNW72M= X-Proofpoint-ORIG-GUID: yCbLIbgJr-VPCC5H1NlajJOC0q085kEC X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDAyMDAzOSBTYWx0ZWRfX6jCu+ZYfCfRV /7l1oOo9fqOnzQ6m3dNIPrnnC/WAjB6tWj92haIQxiz4P/8JeKAhVnoJB/LVKSYaedB8G04VoCV sLE3pA8nP3rln7k+AL3QNxQz0KweJ08n0+h0o/zAyWAAntGuFyJq62bC2hodsAupTLOnX0voebD zWuiXOOPVcDxLJp5Rxjw6HdhYbXBcSvEfR26cHPOSYtR8ptfQ33NMBmG7dTi8OyKs0qoHql2bvD KDZubxHlvz+ENQeCgs4leRoOOGF1hLtS9km/uHgdHXhj9JhFF4pg8Olr91j2F97fsgicfm/KaoN namYizlvEq1JV+xtwapwrP+3OxiFk8/IWnBiW4ntfCSLFZdHUAYJy7cVhZtLlaObl8/poUyLM4c FdoUxZhghGEEoLCrP1f/dezwobnkM5cEXMDE0r5wo6BP590cN8Ut4Dbh0nHkiPrNLCpjUhq5vwn GlMtmoC3YJHhkGY6TcA== X-Authority-Analysis: v=2.4 cv=f+jdl+yM c=1 sm=1 tr=0 ts=6abf7e41 cx=c_pps a=EVbN6Ke/fEF3bsl7X48z0g==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=v9AyLkvIsLCxcgOLbSsA:9 a=QEXdDO2ut3YA:10 a=a_PwQJl-kcHnX1M80qC6:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-02_03,2026-10-01_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 priorityscore=1501 impostorscore=0 suspectscore=0 clxscore=1015 malwarescore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2610020039 On 10/1/26 10:22, Herve Codina (Schneider Electric) wrote: > The Renesas RZ/N1 SoCs family has two timers block controller > available. > > Each controller is charge of 8 timers (six 16-bit timers + two 32-bit > timers). > > Each timer has its own interrupt, its own prescaler that can be used to > divide the clock by 25 (timers block are fed with a 25 MHz clock) and > all timers can work in either one-shot or periodic mode. > > This series adds support for those timers blocks. > > Best regards, Applied, patch 1,2 and 4