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Wed, 03 Jun 2026 05:57:46 -0700 (PDT) Message-ID: <8eb709ce-3469-4303-9c3d-8d1a221cb8de@linaro.org> Date: Wed, 3 Jun 2026 13:57:44 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 2/2] phy: qcom-mipi-csi2: Add a CSI2 MIPI DPHY driver To: Dmitry Baryshkov Cc: Vladimir Zapolskiy , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Bryan O'Donoghue , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260523-x1e-csi2-phy-v8-0-a85668459521@linaro.org> <20260523-x1e-csi2-phy-v8-2-a85668459521@linaro.org> <54904b61-222d-4600-ad4c-c03a9952d337@linaro.org> From: Bryan O'Donoghue Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 03/06/2026 13:40, Dmitry Baryshkov wrote: >> Are you sure about that ? > Yes. > >> ipcat I thought designated lane 7 specifically as clk-lane i.e. named it >> CLK_LN of some description. > Split configurations explicitly use other lanes for clocks. E.g. check > the RB5 Navigation schematics, CAM0B connector. Can you please check: CSI_3PHASE_COMMON.CSI_COMMON_CTRL5 0 LN0_PWRDN_B Lane 0 ... 7 LNCK_PWRDN_B Clock Lane ... just a badly name field CSI_2PHASE_CTRL10 Bit[2] = IS_CLKLANE Right so CSI_2PHASE_CTRL10 controls lane mode, indeed. Thanks for checking. --- bod