From: Kishon Vijay Abraham I <kishon@ti.com>
To: Rob Herring <robh@kernel.org>, Anil Varughese <aniljoy@cadence.com>
Cc: Roger Quadros <rogerq@ti.com>, Jyri Sarha <jsarha@ti.com>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>
Subject: Re: [PATCH v2 01/14] dt-bindings: phy: Sierra: Add bindings for Sierra in TI's J721E
Date: Wed, 30 Oct 2019 11:06:18 +0530 [thread overview]
Message-ID: <8ec5a9bd-4283-04bf-af4c-c5b7b912a342@ti.com> (raw)
In-Reply-To: <20191029185916.GA19313@bogus>
Hi Rob,
On 30/10/19 12:29 AM, Rob Herring wrote:
> On Wed, Oct 23, 2019 at 06:27:22PM +0530, Kishon Vijay Abraham I wrote:
>> Add DT binding documentation for Sierra PHY IP used in TI's J721E
>> SoC.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>> .../devicetree/bindings/phy/phy-cadence-sierra.txt | 13 ++++++++-----
>> 1 file changed, 8 insertions(+), 5 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt
>> index 6e1b47bfce43..bf90ef7e005e 100644
>> --- a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt
>> +++ b/Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt
>> @@ -2,21 +2,24 @@ Cadence Sierra PHY
>> -----------------------
>>
>> Required properties:
>> -- compatible: cdns,sierra-phy-t0
>> -- clocks: Must contain an entry in clock-names.
>> - See ../clocks/clock-bindings.txt for details.
>> -- clock-names: Must be "phy_clk"
>> +- compatible: Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform
>> + Must be "ti,sierra-phy-t0" for Sierra in TI's J721E SoC.
>> - resets: Must contain an entry for each in reset-names.
>> See ../reset/reset.txt for details.
>> - reset-names: Must include "sierra_reset" and "sierra_apb".
>> "sierra_reset" must control the reset line to the PHY.
>> "sierra_apb" must control the reset line to the APB PHY
>> - interface.
>> + interface ("sierra_apb" is optional).
>> - reg: register range for the PHY.
>> - #address-cells: Must be 1
>> - #size-cells: Must be 0
>>
>> Optional properties:
>> +- clocks: Must contain an entry in clock-names.
>> + See ../clocks/clock-bindings.txt for details.
>> +- clock-names: Must be "phy_clk". Must contain "cmn_refclk" and
>> + "cmn_refclk1" for configuring the frequency of the
>> + clock to the lanes.
>
> I don't understand how the same block can have completely different
> clocks. Did the original binding forget some?
>
> TI needs 0, 1 or 3 clocks? Reads like it could be any.
For TI, phy_clk is not needed. Anil, can you clarify what this clock actually
corresponds to? Is it a functional clock of PHY?
Sierra SERDES actually has a number of clocks which can be configured. The
initial dt-binding didn't model all these clocks. The "cmn_refclk" and
"cmn_refclk1" are used to program the dividers withing the Sierra. The actual
registers for programming the dividers are in the Sierra wrapper though. The
original Sierra driver and dt-binding didn't try to change the default divider
values.
Thanks
Kishon
>
> Rob
>
next prev parent reply other threads:[~2019-10-30 5:37 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-23 12:57 [PATCH v2 00/14] PHY: Add support for SERDES in TI's J721E SoC Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 01/14] dt-bindings: phy: Sierra: Add bindings for Sierra in TI's J721E Kishon Vijay Abraham I
2019-10-29 18:59 ` Rob Herring
2019-10-30 5:36 ` Kishon Vijay Abraham I [this message]
2019-11-05 9:40 ` Anil Joy Varughese
2019-10-23 12:57 ` [PATCH v2 02/14] phy: cadence: Sierra: Make "phy_clk" and "sierra_apb" optional resources Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 03/14] phy: cadence: Sierra: Use "regmap" for read and write to Sierra registers Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 04/14] phy: cadence: Sierra: Add support for SERDES_16G used in J721E SoC Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 05/14] phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_ops Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 06/14] phy: cadence: Sierra: Modify register macro names to be in sync with Sierra user guide Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 07/14] phy: cadence: Sierra: Configure both lane cdb and common cdb registers for external SSC Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 08/14] phy: cadence: Sierra: Get reset control "array" for each link Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 09/14] phy: cadence: Sierra: Check for PLL lock during PHY power on Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 10/14] phy: cadence: Sierra: Change MAX_LANES of Sierra to 16 Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 11/14] phy: cadence: Sierra: Set cmn_refclk/cmn_refclk1 frequency to 25MHz Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 12/14] phy: cadence: Sierra: Use correct dev pointer in cdns_sierra_phy_remove() Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 13/14] dt-bindings: phy: Document WIZ (SERDES wrapper) bindings Kishon Vijay Abraham I
2019-10-29 6:53 ` Kishon Vijay Abraham I
2019-10-29 19:08 ` Rob Herring
2019-10-30 5:45 ` Kishon Vijay Abraham I
2019-10-30 19:26 ` Rob Herring
2019-10-31 4:41 ` Kishon Vijay Abraham I
2019-10-23 12:57 ` [PATCH v2 14/14] phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC Kishon Vijay Abraham I
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