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[88.112.128.43]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-32fab8ed35bsm15350211fa.84.2025.07.14.07.13.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 14 Jul 2025 07:13:54 -0700 (PDT) Message-ID: <8ed5eeee-78a2-4b26-989f-03676a9e5da7@linaro.org> Date: Mon, 14 Jul 2025 17:13:48 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/2] dt-bindings: phy: qcom: Add MIPI CSI2 C-PHY/DPHY Combo schema Content-Language: ru-RU To: Bryan O'Donoghue , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Bryan O'Donoghue , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250710-x1e-csi2-phy-v1-0-74acbb5b162b@linaro.org> <20250710-x1e-csi2-phy-v1-1-74acbb5b162b@linaro.org> From: Vladimir Zapolskiy In-Reply-To: <20250710-x1e-csi2-phy-v1-1-74acbb5b162b@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 7/10/25 19:16, Bryan O'Donoghue wrote: > Add a base schema initially compatible with x1e80100 to describe MIPI CSI2 > PHY devices. > > The hardware can support both C-PHY and D-PHY modes. The CSIPHY devices > have their own pinouts on the SoC as well as their own individual voltage > rails. > > The need to model voltage rails on a per-PHY basis leads us to define > CSIPHY devices as individual nodes. > > Two nice outcomes in terms of schema and DT arise from this change. > > 1. The ability to define on a per-PHY basis voltage rails. > 2. The ability to require those voltage. > > We have had a complete bodge upstream for this where a single set of > voltage rail for all CSIPHYs has been buried inside of CAMSS. > > Much like the I2C bus which is dedicated to Camera sensors - the CCI bus in > CAMSS parlance, the CSIPHY devices should be individually modelled. > > Signed-off-by: Bryan O'Donoghue > --- > .../phy/qcom,x1e80100-mipi-csi2-combo-phy.yaml | 95 ++++++++++++++++++++++ > 1 file changed, 95 insertions(+) > > diff --git a/Documentation/devicetree/bindings/phy/qcom,x1e80100-mipi-csi2-combo-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,x1e80100-mipi-csi2-combo-phy.yaml > new file mode 100644 > index 0000000000000000000000000000000000000000..e0976f012516452ae3632ff4732620b5c5402d3b > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom,x1e80100-mipi-csi2-combo-phy.yaml > @@ -0,0 +1,95 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/qcom,x1e80100-mipi-csi2-combo-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm MIPI CSI2 Combo PHY > + > +maintainers: > + - Bryan O'Donoghue > + > +description: > + Qualcomm MIPI CSI2 C-PHY/D-PHY combination PHY. Connects MIPI CSI2 sensors > + to Qualcomm's Camera CSI Decoder. The PHY supports both C-PHY and D-PHY > + modes. > + > +properties: > + compatible: > + const: qcom,x1e80100-mipi-csi2-combo-phy > + > + reg: > + maxItems: 1 > + > + "#phy-cells": > + const: 0 > + > + clocks: > + maxItems: 4 > + > + clock-names: > + items: > + - const: camnoc_axi > + - const: cpas_ahb > + - const: csiphy > + - const: csiphy_timer > + > + interrupts: > + maxItems: 1 > + > + power-domains: > + maxItems: 1 > + > + vdda-0p8-supply: > + description: Phandle to a 0.8V regulator supply to a PHY. > + > + vdda-1p2-supply: > + description: Phandle to 1.2V regulator supply to a PHY. > + > + phy-type: > + description: D-PHY or C-PHY mode > + enum: [ 10, 11 ] > + $ref: /schemas/types.yaml#/definitions/uint32 > + > +required: > + - compatible > + - reg > + - "#phy-cells" > + - clocks > + - clock-names > + - vdda-0p8-supply > + - vdda-1p2-supply > + - phy-type > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + #include > + > + csiphy0: csiphy@ace4000 { > + compatible = "qcom,x1e80100-mipi-csi2-combo-phy"; > + reg = <0x0ace4000 0x2000>; > + #phy-cells = <0>; > + > + clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>, > + <&camcc CAM_CC_CPAS_AHB_CLK>, > + <&camcc CAM_CC_CSIPHY0_CLK>, > + <&camcc CAM_CC_CSI0PHYTIMER_CLK>; > + clock-names = "camnoc_axi", > + "cpas_ahb", > + "csiphy", > + "csiphy_timer"; > + > + interrupts = ; > + > + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; > + > + vdda-0p8-supply = <&vreg_l2c_0p8>; > + vdda-1p2-supply = <&vreg_l1c_1p2>; > + > + phy-type = ; > + }; > There is no ports at all, which makes the device tree node unusable, since you can not provide a way to connect any sensors to the phy. -- Best wishes, Vladimir