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Wed, 12 Mar 2025 09:40:24 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHWKLaYixh5c+sJMPTXs5ZZ3Cbo1u3HxPQsksE8CPOCmdqlu+PjljtTDCDElb5VxtwOAemsfg== X-Received: by 2002:a17:90b:2e42:b0:2f7:7680:51a6 with SMTP id 98e67ed59e1d1-300ff0a4593mr10559656a91.6.1741797624076; Wed, 12 Mar 2025 09:40:24 -0700 (PDT) Received: from [192.168.29.17] ([49.37.215.201]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-30118249759sm2206897a91.25.2025.03.12.09.40.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Mar 2025 09:40:23 -0700 (PDT) Message-ID: <8efdc560-d061-4f03-bed5-8571044119cc@oss.qualcomm.com> Date: Wed, 12 Mar 2025 22:10:17 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1] arm64: dts: qcom: ipq5424: fix and relocate uart1 gpio configurations Content-Language: en-US To: Manikanta Mylavarapu , andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, quic_srichara@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: quic_varada@quicinc.com References: <20250312091418.3265352-1-quic_mmanikan@quicinc.com> From: Kathiravan Thirumoorthy In-Reply-To: <20250312091418.3265352-1-quic_mmanikan@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-ORIG-GUID: Lw87oAZBCge0ALKbnRUGZexbbn8N2AYH X-Proofpoint-GUID: Lw87oAZBCge0ALKbnRUGZexbbn8N2AYH X-Authority-Analysis: v=2.4 cv=TIhFS0la c=1 sm=1 tr=0 ts=67d1b8fb cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=d+lWxUpqeNYAcJEdQAshKg==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=COk6AnOGAAAA:8 a=HwDeC_NjNoN76rn-rm0A:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=qBRm1UoaiinxN4wKqXP-:22 a=rl5im9kqc5Lf4LNbBjHf:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-12_05,2025-03-11_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 mlxlogscore=661 mlxscore=0 clxscore=1015 bulkscore=0 malwarescore=0 suspectscore=0 spamscore=0 phishscore=0 impostorscore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502280000 definitions=main-2503120114 On 3/12/2025 2:44 PM, Manikanta Mylavarapu wrote: > Update the bias configuration for UART1 TX and RX pins to ensure correct > settings for RDP466. > > Additionally, move the UART1 GPIO configurations from the common .dtsi > file to the RDP-specific .dts files to account for differing bias > configurations across RDPs of IPQ5424. > > Fixes: 1a91d2a6021e ("arm64: dts: qcom: add IPQ5424 SoC and rdp466 board support") > Signed-off-by: Manikanta Mylavarapu > --- > arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts | 16 +++++++++++++++- > arch/arm64/boot/dts/qcom/ipq5424.dtsi | 7 ------- > 2 files changed, 15 insertions(+), 8 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts > index b6e4bb3328b3..7b85aaa11ee8 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts > +++ b/arch/arm64/boot/dts/qcom/ipq5424-rdp466.dts > @@ -147,10 +147,24 @@ data-pins { > bias-pull-up; > }; > }; > + > + uart1_tx_state: uart1-tx-state { > + pins = "gpio44"; > + function = "uart1"; > + drive-strength = <8>; > + bias-pull-down; > + }; > + > + uart1_rx_state: uart1-rx-state { > + pins = "gpio43"; > + function = "uart1"; > + drive-strength = <8>; > + bias-pull-up; > + }; > }; > > &uart1 { > - pinctrl-0 = <&uart1_pins>; > + pinctrl-0 = <&uart1_tx_state>, <&uart1_rx_state>; Change LGTM. But can we define both TX and RX pin definition under one node like below, to align with the SPI and SDCC gpio definition layout? qup_uart1_default_state: qup-uart1-default-state {         uart1_tx_state: uart1-tx-state {          ...         };         uart1_rx_state: uart1-rx-state {          ...         }; }; and refer it like pinctrl-0 = <&qup_uart1_default_state>; > pinctrl-names = "default"; > status = "okay"; > }; > diff --git a/arch/arm64/boot/dts/qcom/ipq5424.dtsi b/arch/arm64/boot/dts/qcom/ipq5424.dtsi > index 7a7ad700a382..e190c43c1b11 100644 > --- a/arch/arm64/boot/dts/qcom/ipq5424.dtsi > +++ b/arch/arm64/boot/dts/qcom/ipq5424.dtsi > @@ -262,13 +262,6 @@ tlmm: pinctrl@1000000 { > gpio-ranges = <&tlmm 0 0 50>; > interrupt-controller; > #interrupt-cells = <2>; > - > - uart1_pins: uart1-state { > - pins = "gpio43", "gpio44"; > - function = "uart1"; > - drive-strength = <8>; > - bias-pull-up; > - }; > }; > > gcc: clock-controller@1800000 { > > base-commit: 0a2f889128969dab41861b6e40111aa03dc57014