From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [213.167.242.64]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1343E357CE0 for ; Mon, 22 Jun 2026 07:31:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=213.167.242.64 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782113511; cv=none; b=kqM7ydKKEtK2FoRRZ66GraG4GCxlg81UG0stKttnwEThHNfaF1Cjf95ZOpDce/j12Q+hja9dFEe8TusDJCryzR8BI59p43WLc0rYQ+FER/Z662FeJ4ZHVUCxdupV0PqvlakCmbVrb2ExRqz8G/b+ovfNdwdNBIjk88Ts7M0E1gk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1782113511; c=relaxed/simple; bh=ol+3hMIshApUprdQMTjS1Gy1eVK1KNsU0DKxoEjwVeI=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=W5xuhGzEtBn3RWIX/R5GAPvcF07+HuQB90vv+ztEmloGw9hEA1PUrJfv0bE+rTRVOd8L4/F58qWUuoADY3kO6j1dqeR/wwkUte4weEn0yRrWVutLFV0SncE7qWGQpx7EWiCsoNHUgKEQrm9O44mNmgclqFzYNWaHcGUMs0WGM8w= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com; spf=pass smtp.mailfrom=ideasonboard.com; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b=JnW1sIL9; arc=none smtp.client-ip=213.167.242.64 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ideasonboard.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ideasonboard.com header.i=@ideasonboard.com header.b="JnW1sIL9" Received: from [192.168.88.20] (91-158-153-178.elisa-laajakaista.fi [91.158.153.178]) by perceval.ideasonboard.com (Postfix) with ESMTPSA id 1C94756D; Mon, 22 Jun 2026 09:31:01 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1782113461; bh=ol+3hMIshApUprdQMTjS1Gy1eVK1KNsU0DKxoEjwVeI=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=JnW1sIL9ShNu054CyuWzUl6Hw1srISiWBnzM/vwHN5f4e11kZUPV2RU9rtwb/ZRW3 3s+tYOInYo9COeVavBkr50/robnoVQ6SgdToNPs4cn5XIwiRuujWy/r3fblm1jcBsO 7XLVWvAG3EVjsuhQqPdZzGMfD10nGqqdsVkOJJmc= Message-ID: <8efe44d7-3864-45cb-bd79-f25f573b6432@ideasonboard.com> Date: Mon, 22 Jun 2026 10:31:35 +0300 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 07/13] drm/bridge: tc358762: Update comment about the number of lanes To: Andreas Kemnade Cc: Marek Vasut , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Dave Stevenson References: <20260513-tc358762-fixes-v3-0-6698b55008b9@ideasonboard.com> <20260513-tc358762-fixes-v3-7-6698b55008b9@ideasonboard.com> <20260529203424.72199881@kemnade.info> From: Tomi Valkeinen Content-Language: en-US In-Reply-To: <20260529203424.72199881@kemnade.info> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Hi, On 29/05/2026 21:34, Andreas Kemnade wrote: > On Wed, 13 May 2026 16:10:16 +0300 > Tomi Valkeinen wrote: > >> Update comment about the number of lanes. >> >> Signed-off-by: Tomi Valkeinen >> --- >> drivers/gpu/drm/bridge/tc358762.c | 9 ++++++++- >> 1 file changed, 8 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/bridge/tc358762.c b/drivers/gpu/drm/bridge/tc358762.c >> index 7840ab3454f6..c5734c4df440 100644 >> --- a/drivers/gpu/drm/bridge/tc358762.c >> +++ b/drivers/gpu/drm/bridge/tc358762.c >> @@ -306,7 +306,14 @@ static int tc358762_probe(struct mipi_dsi_device *dsi) >> ctx->dev = dev; >> ctx->pre_enabled = false; >> >> - /* TODO: Find out how to get dual-lane mode working */ >> + /* >> + * When using DSI clk for pixel clock (only mode supported in the driver), >> + * the pclk is derived directly from the DSI byteclk via simple divider, >> + * which is either 2 or 3. >> + * The required divider can be calculated with bitspp / 8 / nlanes. Thus, >> + * for RGB888, only nlanes = 1 works as nlanes = 2 would require divider >> + * of 1.5. >> + */ >> dsi->lanes = 1; >> dsi->format = MIPI_DSI_FMT_RGB888; >> dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_SYNC_PULSE | >> > wondering: I am using lanes = 2 and RGB888. But I need to write something to > SYSPLL3 register. Which somehow is sensitive to write to.... Do you have any > information about that register? If you have an external refclk, then you can use the tc358762 pll to generate the clock, which I guess you are using. SYSPLL3 configures some parts of the PLL, and the doc says the write to SYSPLL3 must be the last in the sequence. Tomi