From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753147AbdEDXAA (ORCPT ); Thu, 4 May 2017 19:00:00 -0400 Received: from mail-db5eur01on0055.outbound.protection.outlook.com ([104.47.2.55]:60918 "EHLO EUR01-DB5-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751900AbdEDW76 (ORCPT ); Thu, 4 May 2017 18:59:58 -0400 From: Han Xu To: Stefan Agner CC: "dwmw2@infradead.org" , "computersforpeace@gmail.com" , "boris.brezillon@free-electrons.com" , "marek.vasut@gmail.com" , "richard@nod.at" , "cyrille.pitchen@atmel.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "shawnguo@kernel.org" , "kernel@pengutronix.de" , "fabio.estevam@freescale.com" , "LW@KARO-electronics.de" , "linux-mtd@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH v2 4/5] ARM: dts: imx7: add GPMI NAND Thread-Topic: [PATCH v2 4/5] ARM: dts: imx7: add GPMI NAND Thread-Index: AQHSuwbg2fq7XKu++UG1x4fvXWlJy6HkngyAgAAs6gCAABJlAA== Date: Thu, 4 May 2017 22:59:52 +0000 Message-ID: <8f039bb6-9bc3-349a-cfe8-727e4caf41de@nxp.com> References: <20170422012338.4635-1-stefan@agner.ch> <20170422012338.4635-5-stefan@agner.ch> <48b5c543e713f9597b67a39a51ffd521@agner.ch> In-Reply-To: <48b5c543e713f9597b67a39a51ffd521@agner.ch> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: agner.ch; dkim=none (message not signed) header.d=none;agner.ch; dmarc=none action=none header.from=nxp.com; x-originating-ip: [192.88.168.1] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;DBXPR04MB077;7:ubhXidmdYWeGL5/CYY6PQMMb69ytDcI6Js9OrXcf9AUfH8/xQQTEZ/hg8EnFClspWQOatpuUj1FoPnugdMPI9+KTumSFIiOpgeM6Z4sUXKN2ZufxKsO6pLm9DoTcZIZDuXfY5lemGLgcWhQ4vRohhbZ4UHxtelQZnUZ8H21IkdJWdbMOUW1R/9uEeZpy4D3EI+NTf/fq056u8VD7AMm0u1c7+kVq1/WapsXKLTuKcFKqqaroGoECSu6zSLf+kqTova4UVA5a45N+PgkWB0sAfLIft8RH9pQXLYW2TEyQUEGRubYWhH5S4XqFg9QvIPqw/AlQ8hI7Pqq6mCh5cQRwSg== x-ms-office365-filtering-correlation-id: 3885c3d9-1eca-4e51-89a2-08d49341462e x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(22001)(2017030254075)(48565401081)(201703131423075)(201703031133081)(201702281549075);SRVR:DBXPR04MB077; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(189930954265078)(45079756050767); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(6040450)(601004)(2401047)(8121501046)(5005006)(93006095)(93001095)(3002001)(10201501046)(6055026)(6041248)(20161123560025)(20161123558100)(20161123555025)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123562025)(20161123564025)(6072148);SRVR:DBXPR04MB077;BCL:0;PCL:0;RULEID:;SRVR:DBXPR04MB077; x-forefront-prvs: 02973C87BC x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(6009001)(39840400002)(39450400003)(39410400002)(39860400002)(39400400002)(39850400002)(377454003)(24454002)(377424004)(76104003)(305945005)(478600001)(7736002)(189998001)(102836003)(6916009)(45080400002)(5660300001)(3846002)(6246003)(38730400002)(2950100002)(86362001)(31696002)(575784001)(110136004)(6116002)(8676002)(8936002)(81166006)(66066001)(3280700002)(33646002)(7416002)(6306002)(93886004)(229853002)(6512007)(36756003)(54356999)(54906002)(39060400002)(3660700001)(53936002)(76176999)(99286003)(25786009)(53546009)(2906002)(6436002)(6486002)(31686004)(4326008)(5250100002)(6506006)(2900100001)(50986999);DIR:OUT;SFP:1101;SCL:1;SRVR:DBXPR04MB077;H:DBXPR04MB080.eurprd04.prod.outlook.com;FPR:;SPF:None;MLV:ovrnspm;PTR:InfoNoRecords;LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="Windows-1252" Content-ID: <7FDEF8E0A9E31246B4C0971E3F6F7D6B@eurprd04.prod.outlook.com> MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 04 May 2017 22:59:52.3144 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBXPR04MB077 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id v44N0NRW027820 On 05/04/2017 04:50 PM, Stefan Agner wrote: > On 2017-05-04 12:13, Han Xu wrote: >> On 04/21/2017 08:23 PM, Stefan Agner wrote: >>> Add i.MX 7 GPMI NAND module. >>> >>> Signed-off-by: Stefan Agner >>> --- >>> arch/arm/boot/dts/imx7s.dtsi | 31 +++++++++++++++++++++++++++++++ >>> 1 file changed, 31 insertions(+) >>> >>> diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi >>> index 843eb379e1ea..9645257638d4 100644 >>> --- a/arch/arm/boot/dts/imx7s.dtsi >>> +++ b/arch/arm/boot/dts/imx7s.dtsi >>> @@ -995,5 +995,36 @@ >>> status = "disabled"; >>> }; >>> }; >>> + >>> + dma_apbh: dma-apbh@33000000 { >>> + compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh"; >>> + reg = <0x33000000 0x2000>; >>> + interrupts = , >>> + , >>> + , >>> + ; >>> + interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; >>> + #dma-cells = <1>; >>> + dma-channels = <4>; >>> + clocks = <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>, >>> + <&clks IMX7D_NAND_ROOT_CLK>; >>> + clock-names = "dma_apbh_bch", "dma_apbh_io"; >>> + }; >> Do you need some patches to enable all clks for APBH DMA? Refer to >> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwork.ozlabs.org%2Fpatch%2F551967%2F&data=01%7C01%7Chan.xu%40nxp.com%7C98493f7e475341dbf67008d49337b441%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0&sdata=FH9k%2FC4VcVCeyidkRgUJ5Ahu4%2B%2FlDAjXVwO0DY7XMhA%3D&reserved=0 >> > Oh I see, with the current code and this device tree we actually only > enable the first clock... But it seems to work in practice... > > What is interesting, the chapter 5.2.5 System Clocks only describes > APBHDMA, and no GPMI module. > > Chapter 9.4 about APBH-Bridge-DMA bridge only specifies "hclk" as clock > sources. > > When looking at the table in chapter 5.2.5, hclk is > NAND_USDHC_BUS_CLK_ROOT > > Module Syste Module Clock Clock Root > APBHDMA apbhdma.hclk NAND_USDHC_BUS_CLK_ROOT > > So my guess is that the actual DMA controller should work fine with > IMX7D_NAND_USDHC_BUS_ROOT_CLK only. It is only the GPMI module which > needs the NAND_ROOT_CLK. My guess is since the APBHDMA controller is > only used for GPMI these days, it has been combined in one module in the > table in chapter 5.2.5. > > So we could actually only specify: > > clocks = <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>; > > Tested with this and NAND seems to work fine. > > Also tested accessing APBHDMA register in U-Boot with > IMX7D_NAND_ROOT_CLK disabled, it worked fine. > > What do you think? Should we go with this? > > This probably even saves power since GPMI's runtime clock management > disables IMX7D_NAND_ROOT_CLK when NAND is idle (according to the > nand_root_clk counter in clk_summary and the root clock register at > 0x3038AA00). It also surprised me how it can work on your side, I remember we made the code change for some purpose, please give me some time I can check if the doc is wrong. > -- > Stefan > >>> + >>> + gpmi: gpmi-nand@33002000{ >>> + compatible = "fsl,imx7d-gpmi-nand"; >>> + #address-cells = <1>; >>> + #size-cells = <1>; >>> + reg = <0x33002000 0x2000>, <0x33004000 0x4000>; >>> + reg-names = "gpmi-nand", "bch"; >>> + interrupts = ; >>> + interrupt-names = "bch"; >>> + clocks = <&clks IMX7D_NAND_ROOT_CLK>, >>> + <&clks IMX7D_NAND_USDHC_BUS_ROOT_CLK>; >>> + clock-names = "gpmi_io", "gpmi_bch_apb"; >>> + dmas = <&dma_apbh 0>; >>> + dma-names = "rx-tx"; >>> + status = "disabled"; >>> + }; >>> }; >>> };