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Tue, 09 Jun 2026 06:23:55 -0700 (PDT) X-Received: by 2002:a05:6a00:808f:b0:838:127d:a167 with SMTP id d2e1a72fcca58-842b0e6bb0bmr19975821b3a.16.1781011434968; Tue, 09 Jun 2026 06:23:54 -0700 (PDT) Received: from [10.92.193.107] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-842828d6bc5sm20261369b3a.43.2026.06.09.06.23.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Jun 2026 06:23:54 -0700 (PDT) Message-ID: <8f045340-a6c8-41c7-b1c7-6d9b87b05d90@oss.qualcomm.com> Date: Tue, 9 Jun 2026 18:53:49 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/3] powercap: qcom: Add SPEL powercap driver To: Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , "Rafael J. Wysocki" , Bjorn Andersson , Konrad Dybcio , Daniel Lezcano Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Gaurav Kohli References: <20260519-qcom_spel_driver_upstream-v1-0-75356d1b7f94@oss.qualcomm.com> <20260519-qcom_spel_driver_upstream-v1-2-75356d1b7f94@oss.qualcomm.com> <7ea2f2cc-ef11-4727-810c-e32e815bd973@oss.qualcomm.com> Content-Language: en-US From: Manaf Meethalavalappu Pallikunhi In-Reply-To: <7ea2f2cc-ef11-4727-810c-e32e815bd973@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: 7QmZjnoky9izgQ91cY8-F-TovHZBJM4d X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjA5MDEyNyBTYWx0ZWRfX3pisoLZcVEb7 u/AhQjQarMwnk80p4Ors5mPQUdRnFa/fV2h1LA0v5WWNYNdN1Rq/J6GgD9+IUtJxmr0wZyaYFVs PTnIWGCFmanxunc048EIy5Yc7O4FuQW6ZHBbgzL/o/fRbON1a2l65boTfWhdqxIgey2P2dU7hbl /RPnAdR6T4+qY1pmoFxtos8P0q8cEyuUE6mdVvBLCRweP/eN9iYbobMOO4UmL/sEtIbwicbB0/q NEGkQPX8DV8Ia7ixST+G0LlFgv0dT3m0drl+94VTPiMFk7ennwWW9Tm1+xqFI9niPsvRNtE9XDt gukPw5KPlx7Qs9FNTIoS2g0nH9+5DoKb6/NO0bd5JFAoEob82tzuQ+su80X7BUtOx5+sFUIAvxI Q5viSDSn+jh4rLY4hbd4h7wBY8C39S0yfPA5m4b9f7/DMoBSEyxTACy/nmwOjxxXaazJIvM6V5P baXjmyL5wmrYAbwTAuQ== X-Authority-Analysis: v=2.4 cv=NKPlPU6g c=1 sm=1 tr=0 ts=6a2813ec cx=c_pps a=m5Vt/hrsBiPMCU0y4gIsQw==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=bEeoLGOZ4EoZlHOPchMA:9 a=QEXdDO2ut3YA:10 a=IoOABgeZipijB_acs4fv:22 X-Proofpoint-ORIG-GUID: 7QmZjnoky9izgQ91cY8-F-TovHZBJM4d X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-09_03,2026-06-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 adultscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 impostorscore=0 malwarescore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605210000 definitions=main-2606090127 Hi Konrad, On 5/21/2026 4:46 PM, Konrad Dybcio wrote: > On 5/19/26 12:49 PM, Manaf Meethalavalappu Pallikunhi wrote: >> The Qualcomm SoC Power and Electrical Limits (SPEL) provides hardware >> based power monitoring and limiting capabilities for various power >> domains including System, SoC, CPU clusters, GPU, and various other >> subsystems. >> >> The driver integrates with the Linux powercap framework, exposing SPEL >> capabilities through powercap sysfs interfaces. >> >> Signed-off-by: Manaf Meethalavalappu Pallikunhi >> --- > > [...] > >> +/* SPEL register bitmasks */ >> +#define ENERGY_STATUS_MASK 0xFFFFFFFF > > GENMASK(m, n), across the other defines too, please > > Then, you can drop the _OFFSET defines as FIELD_PREP/GET/MODIFY > accessors will derive them from the mask > > Please also use lowercase hex, file-wide ACK > > [...] > >> +/* Constraint configuration */ >> +static struct spel_constraint_info constraints[] = { >> + /* SYS domain constraints */ >> + { 0x10, 0x70, BIT(0), SPEL_DOMAIN_SYS, POWER_LIMIT1 }, >> + { 0x14, 0x74, BIT(1), SPEL_DOMAIN_SYS, POWER_LIMIT2 }, >> + { 0x18, 0x78, BIT(2), SPEL_DOMAIN_SYS, POWER_LIMIT3 }, >> + { 0x1C, 0x7C, BIT(3), SPEL_DOMAIN_SYS, POWER_LIMIT4 }, >> + /* SOC domain constraints */ > > "SoC" ACK > > >> +/* Helper functions */ >> +static bool is_pl_valid(struct spel_domain *sd, int pl) >> +{ >> + if (pl < POWER_LIMIT1 || pl >= NR_POWER_LIMITS) >> + return false; >> + return sd->pl_name[pl] ? true : false; > > return !!sd->pl_name[pl] ACK > > [...] > >> +static u64 spel_unit_xlate(struct spel_domain *sd, enum unit_type type, >> + u64 value, int to_raw) >> +{ >> + struct spel_system *sp = sd->sp; >> + u64 units = 1; >> + u64 scale = 1; >> + >> + switch (type) { >> + case POWER_UNIT: >> + units = sp->power_unit; >> + break; >> + case ENERGY_UNIT: >> + scale = ENERGY_UNIT_SCALE; >> + units = sp->energy_unit; >> + break; >> + case TIME_UNIT: >> + units = sp->time_unit; >> + break; >> + default: >> + return value; > > nit: maybe setting units and scale explicitly in each entry could > be better for maintainability, but potayto/potahto ACK > >> +static int spel_register_powercap(struct spel_system *sp) >> +{ >> + struct spel_domain *sd; >> + struct powercap_zone *power_zone = NULL; >> + int nr_pl, ret, i; >> + >> + /* Register SYS domain as parent zone */ >> + for (sd = sp->domains; sd < sp->domains + SPEL_DOMAIN_MAX; sd++) { >> + if (sd->id == SPEL_DOMAIN_SYS) { >> + nr_pl = spel_find_nr_power_limit(sd); >> + >> + power_zone = powercap_register_zone(&sd->power_zone, >> + sp->control_type, sd->name, >> + NULL, &zone_ops, nr_pl, >> + &constraint_ops); >> + if (IS_ERR(power_zone)) { >> + dev_err(sp->dev, "Failed to register power zone %s\n", >> + sd->name); >> + return PTR_ERR(power_zone); >> + } >> + sp->power_zone = power_zone; >> + break; >> + } >> + } >> + >> + if (!power_zone) { > > I believe this is only possible if ARRAY_SIZE(sp->domains) == 0, > but it's not obivous that it's to protect it from that specifically It will also catch a case where domains defined without root domain SPEL_DOMAIN_SYS > > [...] > >> + /* Map spel domain registers (energy counters) */ >> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nodes"); >> + if (!res) { >> + dev_err(dev, "Failed to get nodes resource\n"); >> + return -EINVAL; >> + } >> + sp->node_base = devm_ioremap_resource(dev, res); >> + if (IS_ERR(sp->node_base)) >> + return PTR_ERR(sp->node_base); > > devm_platform_get_and_ioremap_resource() ACK > > [...] > >> +static void spel_remove(struct platform_device *pdev) >> +{ >> + struct spel_system *sp = platform_get_drvdata(pdev); >> + int i; >> + >> + if (!sp) >> + return; >> + >> + /* Unregister in reverse order: children first, then SOC, then SYS */ >> + for (i = SPEL_DOMAIN_MAX - 1; i >= 0; i--) >> + powercap_unregister_zone(sp->control_type, &sp->domains[i].power_zone); > > Could you try adding a devm_ variant of these register functions? Powercap framework doesn't support any devm_* API, you meant add this support in framework in this series ? > > [...] >> +static const struct of_device_id spel_of_match[] = { >> + { .compatible = "qcom,spel" }, > > The compatible must contain a SoC name ACK Thanks, Manaf > > Konrad