From: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <linux-arm-msm@vger.kernel.org>,
Vinod Koul <vkoul@kernel.org>,
Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>,
Rajendra Nayak <quic_rjendra@quicinc.com>
Subject: Re: [PATCH 2/9] soc: qcom: llcc: Update the logic for version info extraction
Date: Fri, 28 Jan 2022 12:59:29 +0530 [thread overview]
Message-ID: <8f0d544f-ea79-9fab-9579-7bdfed6dcf1b@quicinc.com> (raw)
In-Reply-To: <e311b16376329b9e9483fed8ae910a31d0f7bcba.1643353154.git.quic_saipraka@quicinc.com>
On 1/28/2022 12:39 PM, Sai Prakash Ranjan wrote:
> LLCC HW version info is made up of major, branch, minor and echo
> version bits each of which are 8bits. Several features in newer
> LLCC HW are based on the full version rather than just major or
> minor versions such as write-subcache enable which is applicable
> for versions greater than v2.0.0.0 and upcoming write-subcache
> cacheable for SM8450 SoC which is only present in versions v2.1.0.0
> and later, so it makes it easier and cleaner to just directly
> compare with the full version than adding additional major/branch/
> minor/echo version checks. So remove the earlier major version check
> and add full version check for those features.
>
> Signed-off-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
> ---
> drivers/soc/qcom/llcc-qcom.c | 9 ++++-----
> include/linux/soc/qcom/llcc-qcom.h | 4 ++--
> 2 files changed, 6 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c
> index b3a34f117a7c..a06764f16023 100644
> --- a/drivers/soc/qcom/llcc-qcom.c
> +++ b/drivers/soc/qcom/llcc-qcom.c
> @@ -37,7 +37,6 @@
> #define CACHE_LINE_SIZE_SHIFT 6
>
> #define LLCC_COMMON_HW_INFO 0x00030000
> -#define LLCC_MAJOR_VERSION_MASK GENMASK(31, 24)
>
> #define LLCC_COMMON_STATUS0 0x0003000c
> #define LLCC_LB_CNT_MASK GENMASK(31, 28)
> @@ -55,6 +54,8 @@
>
> #define BANK_OFFSET_STRIDE 0x80000
>
> +#define LLCC_VERSION_2_0_0_0 0x02000000
> +
> /**
> * struct llcc_slice_config - Data associated with the llcc slice
> * @usecase_id: Unique id for the client's use case
> @@ -504,7 +505,7 @@ static int _qcom_llcc_cfg_program(const struct llcc_slice_config *config,
> return ret;
> }
>
> - if (drv_data->major_version == 2) {
> + if (drv_data->version >= LLCC_VERSION_2_0_0_0) {
> u32 wren;
>
> wren = config->write_scid_en << config->slice_id;
> @@ -598,13 +599,11 @@ static int qcom_llcc_probe(struct platform_device *pdev)
> goto err;
> }
>
> - /* Extract major version of the IP */
> + /* Extract version of the IP */
> ret = regmap_read(drv_data->bcast_regmap, LLCC_COMMON_HW_INFO, &version);
> if (ret)
> goto err;
>
> - drv_data->major_version = FIELD_GET(LLCC_MAJOR_VERSION_MASK, version);
> -
Sorry, I missed assigning version info to drv_data here in this version.
I am sending a v2 with the fix.
Thanks,
Sai
> ret = regmap_read(drv_data->regmap, LLCC_COMMON_STATUS0,
> &num_banks);
> if (ret)
> diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h
> index 9e8fd92c96b7..beecf00b707d 100644
> --- a/include/linux/soc/qcom/llcc-qcom.h
> +++ b/include/linux/soc/qcom/llcc-qcom.h
> @@ -83,7 +83,7 @@ struct llcc_edac_reg_data {
> * @bitmap: Bit map to track the active slice ids
> * @offsets: Pointer to the bank offsets array
> * @ecc_irq: interrupt for llcc cache error detection and reporting
> - * @major_version: Indicates the LLCC major version
> + * @version: Indicates the LLCC version
> */
> struct llcc_drv_data {
> struct regmap *regmap;
> @@ -96,7 +96,7 @@ struct llcc_drv_data {
> unsigned long *bitmap;
> u32 *offsets;
> int ecc_irq;
> - u32 major_version;
> + u32 version;
> };
>
> #if IS_ENABLED(CONFIG_QCOM_LLCC)
next prev parent reply other threads:[~2022-01-28 7:29 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-28 7:09 [PATCH 0/9] soc: qcom: llcc: Add LLCC support for SM8450 SoC Sai Prakash Ranjan
2022-01-28 7:09 ` [PATCH 1/9] soc: qcom: llcc: Add support for 16 ways of allocation Sai Prakash Ranjan
2022-01-28 7:09 ` [PATCH 2/9] soc: qcom: llcc: Update the logic for version info extraction Sai Prakash Ranjan
2022-01-28 7:29 ` Sai Prakash Ranjan [this message]
2022-01-28 7:09 ` [PATCH 3/9] soc: qcom: llcc: Add write-cache cacheable support Sai Prakash Ranjan
2022-01-28 7:09 ` [PATCH 4/9] soc: qcom: llcc: Add missing llcc configuration data Sai Prakash Ranjan
2022-01-28 7:09 ` [PATCH 5/9] soc: qcom: llcc: Update register offsets for newer LLCC HW Sai Prakash Ranjan
2022-01-28 7:09 ` [PATCH 6/9] soc: qcom: llcc: Add configuration data for SM8450 SoC Sai Prakash Ranjan
2022-01-28 7:09 ` [PATCH 7/9] dt-bindings: arm: msm: Add LLCC compatible for SM8350 Sai Prakash Ranjan
2022-01-28 7:09 ` [PATCH 8/9] dt-bindings: arm: msm: Add LLCC compatible for SM8450 Sai Prakash Ranjan
2022-01-28 7:09 ` [PATCH 9/9] arm64: dts: qcom: sm8450: Add LLCC/system-cache-controller node Sai Prakash Ranjan
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