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Thu, 4 Sep 2025 23:57:35 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55; Thu, 4 Sep 2025 23:57:35 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.55 via Frontend Transport; Thu, 4 Sep 2025 23:57:35 -0500 Received: from [172.24.20.139] (lt5cd2489kgj.dhcp.ti.com [172.24.20.139]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 5854vUAT190793; Thu, 4 Sep 2025 23:57:31 -0500 Message-ID: <8f0dc883-7bab-4ad8-8db2-6c8f8377fdb3@ti.com> Date: Fri, 5 Sep 2025 10:27:30 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 3/3] arm64: dts: ti: k3-pinctrl: Add the remaining macros To: Akashdeep Kaur , , , , , , , , , , , , CC: , , References: <20250902071917.1616729-1-a-kaur@ti.com> <20250902071917.1616729-4-a-kaur@ti.com> <1a20e784-d2d7-46d7-b705-67e460b6ae33@ti.com> Content-Language: en-US From: "Kumar, Udit" In-Reply-To: <1a20e784-d2d7-46d7-b705-67e460b6ae33@ti.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea On 9/4/2025 7:16 PM, Akashdeep Kaur wrote: > Hi Udit, > > On 04/09/25 18:06, Kumar, Udit wrote: >> > > ... > >>> ... >>>>>   #define PULLTYPESEL_SHIFT    (17) >>>>>   #define RXACTIVE_SHIFT        (18) >>>>> +#define DRV_STR_SHIFT           (19) >>>> >>>> referring to above TRM mentioned in commit message >>>> >>>> Bit 20-19 are for DRV_STR, and description says >>>> >>>> 0 - Default >>>> 1 - Reserved >>>> 2 - Reserved >>>> 3 - Reserved >>>> >>>> Not sure, is there some additional document to be referred for >>>> PIN_DRIVE_STRENGTH >>> >>> This information will be updated in TRM in coming cycles. >> >> >> Sorry , >> >> can not ack before TRM update > > The information can be found at > https://www.ti.com/lit/ug/spruj83b/spruj83b.pdf in Table 14-8769. > Description Of The Pad Configuration Register Bit Then please give correct reference in commit message > >> >> >> >>>> >>>> >>>>> +#define DS_ISO_OVERRIDE_SHIFT (22) >>>>> +#define DS_ISO_BYPASS_EN_SHIFT  (23) >>>> > > ... > >>>> >>>>>   /* Default mux configuration for gpio-ranges to use with pinctrl */ >>>>>   #define PIN_GPIO_RANGE_IOPAD    (PIN_INPUT | 7) >>> >>> Regards, >>> Akashdeep Kaur > > Thanks, > Akashdeep Kaur >