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Sun, 04 May 2025 01:49:53 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 5441nqlX031372 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sun, 4 May 2025 01:49:53 GMT Received: from [10.253.79.250] (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Sat, 3 May 2025 18:49:49 -0700 Message-ID: <8f11c588-aba8-4550-9066-c6bdda0416d1@quicinc.com> Date: Sun, 4 May 2025 09:49:46 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/6] dt-bindings: clock: qcom: Add CMN PLL support for IPQ5018 SoC To: , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lee Jones , Konrad Dybcio CC: , , , References: <20250502-ipq5018-cmn-pll-v1-0-27902c1c4071@outlook.com> <20250502-ipq5018-cmn-pll-v1-1-27902c1c4071@outlook.com> Content-Language: en-US From: Jie Luo In-Reply-To: <20250502-ipq5018-cmn-pll-v1-1-27902c1c4071@outlook.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 5dPE0gK7V1J6Fl0RJIc9HPzt403kkICJ X-Authority-Analysis: v=2.4 cv=O7Y5vA9W c=1 sm=1 tr=0 ts=6816c7c1 cx=c_pps a=JYp8KDb2vCoCEuGobkYCKw==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=UqCG9HQmAAAA:8 a=8uU5PDXsy-7Xv9xxr94A:9 a=QEXdDO2ut3YA:10 X-Proofpoint-ORIG-GUID: 5dPE0gK7V1J6Fl0RJIc9HPzt403kkICJ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTA0MDAxNSBTYWx0ZWRfX/Y5n6lCQg8XT VVEtmDk1cyXa8r94sCKSEWW9DQt/AJ106f43p3STZEGtJ4jL8//mkZovoPYGbPShI6d6uh8U24h cl7ZdSk6Zwl7loAEVBzgZmFmBKQ5QGu57UDviz2O18cledn/p8tj8KNwkQzwcO9Usr8ZvwxtkuY pBL+qJ21zunY5fraXNui6umMM7Feb+sTozPF6ltR9b+y4jZqG1AYQVI7UzPSvVh0Y7rpT49P+Jb k37CCi21Gr+roxC1HfVZ+xJopi653QhBRL9OjvR5ZJD/oBSECHsg6XYoEQ2vdiOs+24vTPsOb4o 2UY00bpVuhB1osHnekjKyaX4wobuyJjokt8sBP27ZgNzihNUDyHC2BDf9PzSv/zOKvTY2kNc84O nl4mi2ZvCi368lNJEHtG7SxwTOlQ7G45/8d7UtlwwtfihOTAcqf2iMxEMQfkdBJ7qdGoKnpo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-04_01,2025-04-30_01,2025-02-21_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 malwarescore=0 mlxlogscore=999 mlxscore=0 clxscore=1011 priorityscore=1501 adultscore=0 phishscore=0 bulkscore=0 impostorscore=0 spamscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2504070000 definitions=main-2505040015 On 5/2/2025 6:15 PM, George Moussalem via B4 Relay wrote: > From: George Moussalem > > The CMN PLL block in the IPQ5018 SoC takes 96 MHZ as the reference > input clock. Its output clocks are the XO (24Mhz), sleep (32Khz), and > ethernet (50Mhz) clocks. > > Unlike IPQ9574, the CMN PLL to the ethernet block needs to be enabled > first in IPQ5018. Hence, add optional phandle to TCSR register space > and offset to do so. > > Signed-off-by: George Moussalem > --- > .../devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml | 11 ++++++++--- > include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h | 16 ++++++++++++++++ > 2 files changed, 24 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml > index cb6e09f4247f4b25105b25f4ae746c0b3ef47616..25006d65d30e20ef8e1f43537bcf3dca65bae73d 100644 > --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml > +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml > @@ -24,12 +24,10 @@ description: > properties: > compatible: > enum: > + - qcom,ipq5018-cmn-pll > - qcom,ipq5424-cmn-pll > - qcom,ipq9574-cmn-pll > > - reg: > - maxItems: 1 > - The property 'reg' should not be removed. > clocks: > items: > - description: The reference clock. The supported clock rates include > @@ -50,6 +48,13 @@ properties: > "#clock-cells": > const: 1 > > + qcom,cmn-pll-eth-enable: > + description: Register in TCSR to enable CMN PLL to ethernet > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + - description: phandle of TCSR syscon > + - description: offset of TCSR register to enable CMN PLL to ethernet > + This TCSR should not be a part of CMN PLL, it is the LDO controller for the internal GEPHY in IPQ5018 SoC, which can be moved to a part of GEPHY device. > required: > - compatible > - reg > diff --git a/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h > new file mode 100644 > index 0000000000000000000000000000000000000000..586d1c9b33b374331bef413f543c526212c18494 > --- /dev/null > +++ b/include/dt-bindings/clock/qcom,ipq5018-cmn-pll.h > @@ -0,0 +1,16 @@ > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ > +/* > + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +#ifndef _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H > +#define _DT_BINDINGS_CLK_QCOM_IPQ5018_CMN_PLL_H > + > +/* CMN PLL core clock. */ > +#define IPQ5018_CMN_PLL_CLK 0 > + > +/* The output clocks from CMN PLL of IPQ5018. */ > +#define IPQ5018_XO_24MHZ_CLK 1 > +#define IPQ5018_SLEEP_32KHZ_CLK 2 > +#define IPQ5018_ETH_50MHZ_CLK 3 > +#endif >