Re: [tip: x86/mm] x86/idle: Remove mb() barriers for X86_BUG_CLFLUSH_MONITOR in mwait_idle_with_hints()

[Andrew Cooper <andrew.cooper3@citrix.com>]

On 02/04/2025 11:10 am, tip-bot2 for Andrew Cooper wrote:
> The following commit has been merged into the x86/mm branch of tip:
>
> Commit-ID:     90a22a5f841490790ecb17166633582681d44945
> Gitweb:        https://git.kernel.org/tip/90a22a5f841490790ecb17166633582681d44945
> Author:        Andrew Cooper <andrew.cooper3@citrix.com>
> AuthorDate:    Wed, 02 Apr 2025 10:10:17 +01:00
> Committer:     Ingo Molnar <mingo@kernel.org>
> CommitterDate: Wed, 02 Apr 2025 11:54:51 +02:00
>
> x86/idle: Remove mb() barriers for X86_BUG_CLFLUSH_MONITOR in mwait_idle_with_hints()
>
> The following commit, 12 years ago:
>
>   7e98b7192046 ("x86, idle: Use static_cpu_has() for CLFLUSH workaround, add barriers")
>
> added barriers around the CLFLUSH in mwait_idle_with_hints(), justified with:
>
>   ... and add memory barriers around it since the documentation is explicit
>   that CLFLUSH is only ordered with respect to MFENCE.
>
> The SDM currently states:
>
>   Executions of the CLFLUSH instruction are ordered with respect to each
>   other and with respect to writes, locked read-modify-write instructions,
>   and fence instructions.
>
>   https://web.archive.org/web/20090219054841/http://download.intel.com/design/xeon/specupdt/32033601.pdf

This link isn't the SDM.  Its ...

>
> With footnote 1 reading:
>
>   Earlier versions of this manual specified that executions of the CLFLUSH
>   instruction were ordered only by the MFENCE instruction.  All processors
>   implementing the CLFLUSH instruction also order it relative to the other
>   operations enumerated above.
>
> I.e. The SDM was incorrect at the time, and barriers should not have been
> inserted.  Double checking the original AAI65 errata (not available from
> intel.com any more) shows no mention of barriers either.

... this errata link, no longer hosted on intel.com.

~Andrew