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From: AngeloGioacchino Del Regno  <angelogioacchino.delregno@collabora.com>
To: Hsiao Chien Sung <shawn.sung@mediatek.com>,
	Chun-Kuang Hu <chunkuang.hu@kernel.org>,
	CK Hu <ck.hu@mediatek.com>
Cc: Philipp Zabel <p.zabel@pengutronix.de>,
	David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Chen-Yu Tsai <wenst@chromium.org>, Sean Paul <sean@poorly.run>,
	Fei Shao <fshao@chromium.org>,
	Bibby Hsieh <bibby.hsieh@mediatek.com>,
	dri-devel@lists.freedesktop.org,
	linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v4 05/17] drm/mediatek: Set DRM mode configs accordingly
Date: Tue, 12 Dec 2023 14:27:20 +0100	[thread overview]
Message-ID: <8f2c5728-0be2-415e-bccb-798c4a22e853@collabora.com> (raw)
In-Reply-To: <20231212121957.19231-6-shawn.sung@mediatek.com>

Il 12/12/23 13:19, Hsiao Chien Sung ha scritto:
> Set DRM mode configs limitation accroding to the
> hardware capabilities.
> 
> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
> ---
>   drivers/gpu/drm/mediatek/mtk_drm_drv.c | 28 ++++++++++++++++++--------
>   drivers/gpu/drm/mediatek/mtk_drm_drv.h |  1 +
>   2 files changed, 21 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 5d551bff6b3f..a4b740420ebb 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -304,6 +304,7 @@ static const struct mtk_mmsys_driver_data mt8188_vdosys0_driver_data = {
>   	.conn_routes = mt8188_mtk_ddp_main_routes,
>   	.conn_routes_num = ARRAY_SIZE(mt8188_mtk_ddp_main_routes),
>   	.mmsys_dev_num = 2,
> +	.max_pitch = GENMASK(15, 0),
>   };
>   
>   static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
> @@ -318,6 +319,7 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
>   	.main_path = mt8195_mtk_ddp_main,
>   	.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
>   	.mmsys_dev_num = 2,
> +	.max_pitch = GENMASK(15, 0),
>   };
>   
>   static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
> @@ -325,6 +327,7 @@ static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
>   	.ext_len = ARRAY_SIZE(mt8195_mtk_ddp_ext),
>   	.mmsys_id = 1,
>   	.mmsys_dev_num = 2,
> +	.max_pitch = GENMASK(15, 0),
>   };
>   
>   static const struct of_device_id mtk_drm_of_ids[] = {
> @@ -463,16 +466,16 @@ static int mtk_drm_kms_init(struct drm_device *drm)
>   	if (ret)
>   		goto put_mutex_dev;
>   
> -	drm->mode_config.min_width = 64;
> -	drm->mode_config.min_height = 64;
> -
>   	/*
> -	 * set max width and height as default value(4096x4096).
> -	 * this value would be used to check framebuffer size limitation
> -	 * at drm_mode_addfb().
> +	 * Set default values for drm mode config
> +	 * these values will be referenced by drm_mode_addfb() as
> +	 * frame buffer size limitation.
>   	 */
> -	drm->mode_config.max_width = 4096;
> -	drm->mode_config.max_height = 4096;
> +	drm->mode_config.min_width = 1;
> +	drm->mode_config.min_height = 1;
> +	drm->mode_config.cursor_width = 512;
> +	drm->mode_config.cursor_height = 512;
> +
>   	drm->mode_config.funcs = &mtk_drm_mode_config_funcs;
>   	drm->mode_config.helper_private = &mtk_drm_mode_config_helpers;
>   
> @@ -502,6 +505,15 @@ static int mtk_drm_kms_init(struct drm_device *drm)
>   		for (j = 0; j < private->data->mmsys_dev_num; j++) {
>   			priv_n = private->all_drm_private[j];
>   
> +			if (priv_n->data->max_pitch) {
> +				/* Save 4 bytes for the color depth (pitch = width x bpp) */

This comment is confusing. Did you mean 4 *bits*? Four bytes is 32 bits.

Also, I'd change the last part to "(pitch = [ width or height ] x bpp)"

> +				drm->mode_config.max_width  = priv_n->data->max_pitch >> 2;
> +				drm->mode_config.max_height = priv_n->data->max_pitch >> 2;
> +			} else {
> +				drm->mode_config.max_width = 4096;
> +				drm->mode_config.max_height = 4096;
> +			}
> +
>   			if (i == 0 && priv_n->data->main_len) {
>   				ret = mtk_drm_crtc_create(drm, priv_n->data->main_path,
>   							  priv_n->data->main_len, j,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index d2efd715699f..3d6c1f58a7ec 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -41,6 +41,7 @@ struct mtk_mmsys_driver_data {
>   	bool shadow_register;
>   	unsigned int mmsys_id;
>   	unsigned int mmsys_dev_num;
> +	u32 max_pitch;

Is it expected to have a max_pitch > 0xFFFF on newer SoCs?
If not, please change this to u16.

Regards,
Angelo

  reply	other threads:[~2023-12-12 13:27 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-12 12:19 [PATCH v4 00/17] Support IGT in display driver Hsiao Chien Sung
2023-12-12 12:19 ` [PATCH v4 01/17] soc: mediatek: Add register definitions for GCE Hsiao Chien Sung
2023-12-12 12:19 ` [PATCH v4 02/17] soc: mediatek: Disable 9-bit alpha in ETHDR Hsiao Chien Sung
2023-12-12 12:19 ` [PATCH v4 03/17] dt-bindings: display: mediatek: ovl: Modify rules for MT8195/MT8188 Hsiao Chien Sung
2023-12-12 13:27   ` AngeloGioacchino Del Regno
2023-12-12 12:19 ` [PATCH v4 04/17] drm/mediatek: Add OVL compatible name for MT8195 Hsiao Chien Sung
2023-12-12 13:27   ` AngeloGioacchino Del Regno
2023-12-12 12:19 ` [PATCH v4 05/17] drm/mediatek: Set DRM mode configs accordingly Hsiao Chien Sung
2023-12-12 13:27   ` AngeloGioacchino Del Regno [this message]
2024-01-02  3:36   ` CK Hu (胡俊光)
2023-12-12 12:19 ` [PATCH v4 06/17] drm/mediatek: Support alpha blending in OVL Hsiao Chien Sung
2024-01-02  5:43   ` CK Hu (胡俊光)
2023-12-12 12:19 ` [PATCH v4 07/17] drm/mediatek: Support alpha blending in Mixer Hsiao Chien Sung
2024-01-02  5:54   ` CK Hu (胡俊光)
2023-12-12 12:19 ` [PATCH v4 08/17] drm/mediatek: Support alpha blending in display driver Hsiao Chien Sung
2024-01-02  6:13   ` CK Hu (胡俊光)
2023-12-12 12:19 ` [PATCH v4 09/17] drm/mediatek: Support CSC in OVL Hsiao Chien Sung
2024-01-02  7:14   ` CK Hu (胡俊光)
2023-12-12 12:19 ` [PATCH v4 10/17] drm/mediatek: Support more color formats " Hsiao Chien Sung
2024-01-02  7:25   ` CK Hu (胡俊光)
2023-12-12 12:19 ` [PATCH v4 11/17] drm/mediatek: Turn off the layers with zero width or height Hsiao Chien Sung
2023-12-12 13:27   ` AngeloGioacchino Del Regno
2023-12-12 12:19 ` [PATCH v4 12/17] drm/mediatek: Support CRC in display driver Hsiao Chien Sung
2024-01-02  8:04   ` CK Hu (胡俊光)
2023-12-12 12:19 ` [PATCH v4 13/17] drm/mediatek: Support CRC in OVL Hsiao Chien Sung
2023-12-12 12:19 ` [PATCH v4 14/17] drm/mediatek: Support CRC in OVL adaptor Hsiao Chien Sung
2023-12-12 12:19 ` [PATCH v4 15/17] drm/mediatek: Add missing plane settings when async update Hsiao Chien Sung
2023-12-12 12:19 ` [PATCH v4 16/17] drm/mediatek: Fix errors when reporting rotation capability Hsiao Chien Sung
2024-01-02  8:26   ` CK Hu (胡俊光)
2023-12-12 12:19 ` [PATCH v4 17/17] drm/mediatek: Add comments for the structures Hsiao Chien Sung
2023-12-12 13:27   ` AngeloGioacchino Del Regno
2024-02-01 10:16 ` [PATCH v4 00/17] Support IGT in display driver AngeloGioacchino Del Regno
2024-02-02  9:03   ` Shawn Sung (宋孝謙)

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