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From: Robin Murphy <robin.murphy@arm.com>
To: Will Deacon <will@kernel.org>, "feng.zhou" <realsummitzhou@gmail.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
	suzuki.poulose@arm.com
Subject: Re: [QUESTION] ARM DSU PMU: 32-bit counter assumption and handling of 64-bit event counters
Date: Thu, 12 Mar 2026 14:51:16 +0000	[thread overview]
Message-ID: <8f72b0f2-d517-4ac6-a593-3b654ac6344d@arm.com> (raw)
In-Reply-To: <abLNm2gs8qszYVWK@willie-the-truck>

On 2026-03-12 2:28 pm, Will Deacon wrote:
> [+Robin and Suzuki]
> 
> On Fri, Feb 06, 2026 at 11:51:38AM +0800, feng.zhou wrote:
>> Hi Will and Mark,
>>
>> I have a question regarding the ARM DSU PMU driver implementation in
>> drivers/perf/arm_dsu_pmu.c, specifically about the counter width
>> assumptions.
>>
>> Current Implementation:
>> ======================
>> The driver currently assumes all event counters are 32-bit wide, with
>> only the cycle counter being 64-bit (lines 69-71):
>>
>> /* All event counters are 32bit, with a 64bit Cycle counter */
>> #define DSU_PMU_COUNTER_WIDTH(idx)	\
>> 	(((idx) == DSU_PMU_IDX_CYCLE_COUNTER) ? 64 : 32)
>>
>> This assumption is used throughout the code for handling counter
>> overflow and calculating deltas (e.g., line 344 in dsu_pmu_event_update).
>>
>> Issue Observed:
>> ===============
>> I've encountered overflow issues when using perf tools on newer ARM CPUs
>> where the event counters appear to be 64-bit rather than 32-bit. The
>> current implementation causes incorrect event counting and potential data
>> loss due to premature overflow handling based on the 32-bit mask.
> 
> I suspect either the hardware or the architecture have evolved since the
> driver was initially written, possibly in a non-backwards-compatible way
> which is why you see problems.
> 
>> Questions:
>> ==========
>> 1. Is the 32-bit event counter assumption based on the ARMv8 PMU
>>     specification or DSU-specific hardware documentation?
>>
>> 2. Are there known ARM CPU implementations where DSU event counters
>>     exceed 32 bits? If so, how should the driver handle this variation?
>>
>> 3. Would it be appropriate to detect the actual counter width at runtime
>>     (similar to how num_counters is probed in dsu_pmu_probe_pmu), or
>>     should this be handled through device tree / ACPI properties?
>>
>> 4. Should there be a mechanism to query the hardware for the actual
>>     counter width to ensure compatibility with future implementations?
>>
>> Thank you for your time and any insights you can provide.
> 
> Suzuki and Robin should be able to help with these...

Yup, indeed newer DSUs subtly evolved, and the patches are already in 
7.0-rc ;)

Cheers,
Robin.

      reply	other threads:[~2026-03-12 14:51 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-02-06  3:51 feng.zhou
2026-03-12 14:28 ` Will Deacon
2026-03-12 14:51   ` Robin Murphy [this message]

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