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Wed, 07 Oct 2026 02:54:01 -0700 (PDT) X-Received: by 2002:a17:90b:4a41:b0:3a0:4384:adf6 with SMTP id 98e67ed59e1d1-3a89f43624amr1437320a91.0.1791366840551; Wed, 07 Oct 2026 02:54:00 -0700 (PDT) Received: from [10.218.18.193] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3a8a60e5166sm1300131a91.4.2026.10.07.02.53.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 07 Oct 2026 02:54:00 -0700 (PDT) Message-ID: <8f75db55-66b2-4b94-b0bd-ccc52f08d197@oss.qualcomm.com> Date: Wed, 7 Oct 2026 15:23:52 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/4] ASoC: cdns: Add Cadence I2S-MC controller driver To: joakim.zhang@cixtech.com, lgirdwood@gmail.com, broonie@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, perex@perex.cz, tiwai@suse.com, p.zabel@pengutronix.de Cc: cix-kernel-upstream@cixtech.com, linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ajay.nandam@oss.qualcomm.com References: <20260928053613.2158446-1-joakim.zhang@cixtech.com> <20260928053613.2158446-5-joakim.zhang@cixtech.com> Content-Language: en-US From: Ajay Kumar Nandam In-Reply-To: <20260928053613.2158446-5-joakim.zhang@cixtech.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: z4mK7ytPk_8zn1Q4t59vV4dYUCSlJy0n X-Proofpoint-GUID: z4mK7ytPk_8zn1Q4t59vV4dYUCSlJy0n X-Authority-Analysis: v=2.4 cv=Xt5vqlF9 c=1 sm=1 tr=0 ts=6ac616ba cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=TAThrSAKAAAA:8 a=Krqe4lgBS7SFU2rUEjIA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 a=8BaDVV8zVhUtoWX9exhy:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA3MDAzOSBTYWx0ZWRfX4M31YiG67ynX xtWo3BC9zKvlqGggPetzd5U+XlfrFSxpxg4sE6nnfvRpYdcpYCoU/X1qhiMiNt8wUZaUWrF6Z3D BLUghenCxocbi4iESbmE5L8k9Id0i9Q6cliher8dvDOgbs4ifrArcYQyjd8t+pMJhBVsrl8JPSg uwv9tyGxnc6djxIXU2KKoomdKoNvKhkQWOWb6LA6AWoJfOJ0v3ii4qRyV45ePkXFCOOMYoPn6PE bLfmSfVadNzvhFkOYf4rZiI3qMTa7R9UKml5HzV+QyXVkVNIG5QgEFw06NgiP9exJg+1uD18L4K mqzx3r7rxKI0notF7dlpeyUsnyahhyYcmy0pu1sjqzA8ZKzeoCYgqlN2rH4NVjfpiOBOIA+FaSs aGvCHPj7mDMe7JVUiPdahYXpsp1RpGM1cKaTq0xlAE+RpOMVdMRUIPOVtULmxRKk+6HXKWeLxkq FYJ19LCV7xUlofPGYbQ== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA3MDAzOSBTYWx0ZWRfX3Cx4fFV9yqxu bD5dxg36SnJFvwzXbikWE0dEtE1REgpJCjpVzkuIMAumeFk06LZWb71KIebAIt8XR0NZhsTI1pK iruueDr4gQ7iQRLkGx9H47CzHw/zDjg= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-07_03,2026-10-06_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 malwarescore=0 clxscore=1015 phishscore=0 impostorscore=0 suspectscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2610070039 On 9/28/2026 11:06 AM, joakim.zhang@cixtech.com wrote: > From: Joakim Zhang > > Add support for the Cadence I2S-MC multi-channel controller found in > the CIX SKY1 audio subsystem. > > The controller moves up to 16 channels through a configurable set of > its 8 data pins, each pin carrying two slots. Wired-out pins may sit > at any pin index and are described by cix,pin-out-num, cix,pin-rx-mask > and cix,pin-tx-mask. The driver exposes a transmit DAI and a receive > DAI which can act as clock provider or consumer independently, and > streams with fewer channels than the wired pins narrow the enabled > pin mask at runtime. > > The driver registers the dmaengine PCM helper, selects the audio > reference clock parent for the 8 kHz or 11.025 kHz sample rate family > and keeps the minimum functional-clock to bit-clock ratio required > for safe clock domain crossing, with an extra margin cycle when the > bit clock is sourced externally. Runtime and system suspend/resume > restore the registers through the regcache. > > Signed-off-by: Joakim Zhang > --- > +static void cdns_i2s_mc_rxtx_config(struct cdns_i2s_mc_priv *i2s_mc_priv, bool on, > + u8 pin_mask, u32 strobe, u32 sync_rst) > +{ > + u32 irq_mask = 0, clk_mask = 0, i2s_mask = 0; > + > + irq_mask |= FIELD_PREP(I2S_CID_CTRL_I2S_MASK, pin_mask); > + > + clk_mask |= FIELD_PREP(I2S_CID_CTRL_I2S_STROBE, pin_mask) | strobe; > + > + i2s_mask |= FIELD_PREP(I2S_CTRL_I2S_EN, pin_mask); > + This patch has the same build issue as the SC driver patch: cdns-i2s-mc.c uses FIELD_PREP() but does not include . ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0); > + if (ret) > + return dev_err_probe(&pdev->dev, ret, > + "Failed to register dmaengine component\n"); > + > + pm_runtime_get_noresume(&pdev->dev); > + pm_runtime_set_active(&pdev->dev); > + ret = devm_pm_runtime_enable(&pdev->dev); > + if (ret) > + return dev_err_probe(&pdev->dev, ret, "Failed to enable runtime PM\n"); > + > + ret = cdns_i2s_mc_clks_enable(i2s_mc_priv); > + if (ret) { > + dev_err_probe(&pdev->dev, ret, "Failed to enable clocks\n"); > + pm_runtime_put_noidle(&pdev->dev); > + return ret; > + } > + > + cdns_i2s_mc_rst(i2s_mc_priv); > + > + irq = platform_get_irq(pdev, 0); > + if (irq < 0) > + return irq; > + i2s_mc_priv->irq = irq; > + > + ret = devm_request_irq(&pdev->dev, irq, cdns_i2s_mc_isr, 0, > + dev_name(&pdev->dev), i2s_mc_priv); > + if (ret) { > + dev_err(&pdev->dev, "Failed to request irq: %d\n", ret); > + pm_runtime_put_noidle(&pdev->dev); > + return ret; > + } After cdns_i2s_mc_clks_enable() succeeds, the platform_get_irq() failure path returns directly without disabling the clocks or dropping the runtime PM usage count. The devm_request_irq() failure path also calls pm_runtime_put_noidle(), but that will not run the runtime suspend callback, so the clocks enabled manually above remain prepared/enabled. Thanks Ajay Kumar Nandam > + > + /* > + * Let pm_runtime_put_sync() disable the clocks, and take regcache effect. > + * If CONFIG_PM is not enabled, the clock will stay powered.