From: "Liang, Kan" <kan.liang@linux.intel.com>
To: Dapeng Mi <dapeng1.mi@linux.intel.com>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Andi Kleen <ak@linux.intel.com>,
Eranian Stephane <eranian@google.com>
Cc: linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
Dapeng Mi <dapeng1.mi@intel.com>
Subject: Re: [PATCH 2/2] perf/x86/intel: Fix wrong index calculation in intel_pmu_config_acr()
Date: Thu, 29 May 2025 09:55:09 -0400 [thread overview]
Message-ID: <8f94b5b7-0552-4860-8ff1-bec83e3abb3e@linux.intel.com> (raw)
In-Reply-To: <20250529080236.2552247-2-dapeng1.mi@linux.intel.com>
On 2025-05-29 4:02 a.m., Dapeng Mi wrote:
> To calculate fixed counter MSR address, the HW counter index "idx" is
> subtracted by INTEL_PMC_IDX_FIXED. It leads to the ACR mask value of
> fixed counters is incorrectly saved to the positions of GP counters
> in acr_cfg_b[], e.g. For fixed counter 0, its ACR counter mask should be
> saved to acr_cfg_b[32], but it's saved to acr_cfg_b[0] incorrectly.
>
> Fix this issue.
>
> Fixes: ec980e4facef ("perf/x86/intel: Support auto counter reload")
> Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Thanks,
Kan
> ---
> arch/x86/events/intel/core.c | 8 +++++---
> 1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index 8d046b1a237e..b0fee684ec8c 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -2899,6 +2899,7 @@ static void intel_pmu_config_acr(int idx, u64 mask, u32 reload)
> {
> struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
> int msr_b, msr_c;
> + int msr_offset;
>
> if (!mask && !cpuc->acr_cfg_b[idx])
> return;
> @@ -2906,19 +2907,20 @@ static void intel_pmu_config_acr(int idx, u64 mask, u32 reload)
> if (idx < INTEL_PMC_IDX_FIXED) {
> msr_b = MSR_IA32_PMC_V6_GP0_CFG_B;
> msr_c = MSR_IA32_PMC_V6_GP0_CFG_C;
> + msr_offset = x86_pmu.addr_offset(idx, false);
> } else {
> msr_b = MSR_IA32_PMC_V6_FX0_CFG_B;
> msr_c = MSR_IA32_PMC_V6_FX0_CFG_C;
> - idx -= INTEL_PMC_IDX_FIXED;
> + msr_offset = x86_pmu.addr_offset(idx - INTEL_PMC_IDX_FIXED, false);
> }
>
> if (cpuc->acr_cfg_b[idx] != mask) {
> - wrmsrl(msr_b + x86_pmu.addr_offset(idx, false), mask);
> + wrmsrl(msr_b + msr_offset, mask);
> cpuc->acr_cfg_b[idx] = mask;
> }
> /* Only need to update the reload value when there is a valid config value. */
> if (mask && cpuc->acr_cfg_c[idx] != reload) {
> - wrmsrl(msr_c + x86_pmu.addr_offset(idx, false), reload);
> + wrmsrl(msr_c + msr_offset, reload);
> cpuc->acr_cfg_c[idx] = reload;
> }
> }
next prev parent reply other threads:[~2025-05-29 13:55 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-29 8:02 [PATCH 1/2] perf/x86/intel: Fix IA32_PMC_x_CFG_B MSRs access error Dapeng Mi
2025-05-29 8:02 ` [PATCH 2/2] perf/x86/intel: Fix wrong index calculation in intel_pmu_config_acr() Dapeng Mi
2025-05-29 13:55 ` Liang, Kan [this message]
2025-05-31 8:25 ` [tip: perf/urgent] perf/x86/intel: Fix incorrect MSR index calculations " tip-bot2 for Dapeng Mi
2025-05-29 13:54 ` [PATCH 1/2] perf/x86/intel: Fix IA32_PMC_x_CFG_B MSRs access error Liang, Kan
2025-05-31 8:01 ` Ingo Molnar
2025-06-03 2:14 ` Mi, Dapeng
2025-06-19 1:11 ` Mi, Dapeng
2025-07-11 2:40 ` Mi, Dapeng
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