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Mon, 29 Jul 2024 18:28:46 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 46TISiOo006559 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 29 Jul 2024 18:28:44 GMT Received: from [10.134.71.247] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Mon, 29 Jul 2024 11:28:44 -0700 Message-ID: <8fa86c0c-183b-4787-9525-38dfe6bcecc6@quicinc.com> Date: Mon, 29 Jul 2024 11:28:35 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] drm/msm/dp: fix the max supported bpp logic To: Stephen Boyd , Daniel Vetter , "David Airlie" , Dmitry Baryshkov , Guenter Roeck , Marijn Suijten , Rob Clark , Sean Paul , Tanmay Shah , Vara Reddy , CC: , , , , , Rob Clark , "Chandan Uddaraju" , , References: <20240725220320.130916-1-quic_abhinavk@quicinc.com> Content-Language: en-US From: Abhinav Kumar In-Reply-To: Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: dYymbe-59TNSP4-xzxgpWlPlCA8jceAr X-Proofpoint-ORIG-GUID: dYymbe-59TNSP4-xzxgpWlPlCA8jceAr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-07-29_16,2024-07-26_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 mlxlogscore=999 malwarescore=0 bulkscore=0 phishscore=0 clxscore=1015 mlxscore=0 spamscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2407290124 Hi Stephen On 7/26/2024 5:24 PM, Stephen Boyd wrote: > Quoting Abhinav Kumar (2024-07-25 15:03:19) >> diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c >> index a916b5f3b317..56ce5e4008f8 100644 >> --- a/drivers/gpu/drm/msm/dp/dp_panel.c >> +++ b/drivers/gpu/drm/msm/dp/dp_panel.c >> @@ -423,8 +424,10 @@ int dp_panel_init_panel_info(struct dp_panel *dp_panel) >> drm_mode->clock); >> drm_dbg_dp(panel->drm_dev, "bpp = %d\n", dp_panel->dp_mode.bpp); >> >> - dp_panel->dp_mode.bpp = max_t(u32, 18, >> - min_t(u32, dp_panel->dp_mode.bpp, 30)); >> + max_supported_bpp = dp_panel_get_mode_bpp(dp_panel, dp_panel->dp_mode.bpp, >> + dp_panel->dp_mode.drm_mode.clock); >> + dp_panel->dp_mode.bpp = max_t(u32, 18, max_supported_bpp); > > Is the max_t() usage still required once 'max_supported_bpp' is also a > u32? Also, what is 18? Shouldn't that be some sort of define so we know > what it represents? > > Or maybe none of that is required? From what I can tell, > dp_panel_get_mode_bpp() calls dp_panel_get_supported_bpp() which will > essentially clamp the bpp range between 18 and 30, unless > dp_panel->dp_mode.bpp is between 30 and 18 but not divisible by 6, e.g. > 29. Perhaps this patch can be included and the max_t above dropped. > > ---8<-- > diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c > b/drivers/gpu/drm/msm/dp/dp_panel.c > index 07db8f37cd06..5cd7c138afd3 100644 > --- a/drivers/gpu/drm/msm/dp/dp_panel.c > +++ b/drivers/gpu/drm/msm/dp/dp_panel.c > @@ -90,22 +90,22 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel) > static u32 dp_panel_get_supported_bpp(struct dp_panel *dp_panel, > u32 mode_edid_bpp, u32 mode_pclk_khz) > { > - struct dp_link_info *link_info; > + const struct dp_link_info *link_info; > const u32 max_supported_bpp = 30, min_supported_bpp = 18; > - u32 bpp = 0, data_rate_khz = 0; > + u32 bpp, data_rate_khz; > > bpp = min_t(u32, mode_edid_bpp, max_supported_bpp); > > link_info = &dp_panel->link_info; > data_rate_khz = link_info->num_lanes * link_info->rate * 8; > > - while (bpp > min_supported_bpp) { > + do { > if (mode_pclk_khz * bpp <= data_rate_khz) > - break; > + return bpp; > bpp -= 6; > - } > + } while (bpp > min_supported_bpp); > > - return bpp; > + return min_supported_bpp; > } > Thanks for the feedback. Your change looks valid. We can use this and drop the max_t usage. Let me push this with your Suggested-by credits. > static int dp_panel_update_modes(struct drm_connector *connector,