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Wed, 11 Dec 2024 00:40:15 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 4BB0eE6E022702 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 11 Dec 2024 00:40:14 GMT Received: from hu-pkondeti-hyd (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 10 Dec 2024 16:40:09 -0800 Date: Wed, 11 Dec 2024 06:10:06 +0530 From: Pavan Kondeti To: Connor Abbott CC: Akhil P Oommen , Rob Clark , Sean Paul , Konrad Dybcio , Abhinav Kumar , "Dmitry Baryshkov" , Marijn Suijten , David Airlie , "Simona Vetter" , Elliot Berman , "Pavan Kondeti" , , , , , Subject: Re: [PATCH] drm/msm/a6xx: Skip gpu secure fw load in EL2 mode Message-ID: <8fc505a0-91ad-4188-8627-fa28fc73a2ae@quicinc.com> References: <20241209-drm-msm-kvm-support-v1-1-1c983a8a8087@quicinc.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: PvmUjKDOnqJZQma83MfyC6K3d2j27XMo X-Proofpoint-ORIG-GUID: PvmUjKDOnqJZQma83MfyC6K3d2j27XMo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 clxscore=1011 suspectscore=0 mlxscore=0 priorityscore=1501 phishscore=0 mlxlogscore=980 spamscore=0 malwarescore=0 bulkscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2412110002 On Tue, Dec 10, 2024 at 05:52:27PM -0500, Connor Abbott wrote: > On Mon, Dec 9, 2024 at 3:20 AM Akhil P Oommen wrote: > > > > When kernel is booted in EL2, SECVID registers are accessible to the > > KMD. So we can use that to switch GPU's secure mode to avoid dependency > > on Zap firmware. Also, we can't load a secure firmware without a > > hypervisor that supports it. > > > > Tested following configurations on sa8775p chipset (Adreno 663 gpu): > > > > 1. Gunyah (No KVM) - Loads zap shader based on DT > > 2. KVM in VHE - Skips zap shader load and programs SECVID register > > 3. KVM in nVHE - Loads zap shader based on DT > > 4. Kernel in EL2 with CONFIG_KVM=n - Skips zap shader load and > > programs SECVID register > > > > For (1) and (3) configuration, this patch doesn't have any impact. > > Driver loads secure firmware based on other existing hints. > > > > Signed-off-by: Akhil P Oommen > > For initializing CX_MISC_SW_FUSE_VALUE in a7xx_cx_mem_init(), we used > !qcom_scm_is_available() to assume that the register is writable > instead - can you just do that? > qcom_scm_is_avaialble() returns true as most of the QC TZ firmware API works w/ kernel running as bare metal i.e booted with EL2. Any services that assume QC firmware @ EL2 (QHEE) is absent. Thanks, Pavan