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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA3MDE0NSBTYWx0ZWRfX+4kdXarLuYg6 H+kzjK6J+MIzaVfaQkT2BMzGDf+CctchfUpLxXkn1+vOfYzlwvX0BEhOQy+Fj+UzZv4a4Eihv9a uqxImlBQHgU7HSnA7YCot96ROIGq8s1O3wuO/S5Ppme2VEEWe3Xx50ww949B9ARTvlDsgiMTcbY EnwozeYtZLblg/UTYGqcIU/fv5R9GmME3xG9zkFWE0DFcn61Fj2b6ygLkhaVBtJyzhqCUPLKT5I V6D8wI/1D1VSn7aqu3j9RZ73bTxfZ1hgwqtu+p8J19x++ebPydq+H+Ivti2ARwylRZPIo6lJWpE DYzkKx9WcNuROPGS0MxasU4ANBuYrTm1WaqXqdL2W6SEBq/5u0GKSg7o7roMZTNuqzTa0Nu6TpI MuPw/iqAqLMWDcw/zLMrn0IeVnQ6OIFErnWdbXyQZ0tpQlHotM1xZ8yGCoz3/I11rRfjZOSFz6T EdOJH1R5MZdw03Cmwxg== X-Proofpoint-ORIG-GUID: pjHu_2GGtu8FPCFHDFztDVjv-CEQDVeT X-Proofpoint-GUID: pjHu_2GGtu8FPCFHDFztDVjv-CEQDVeT X-Authority-Analysis: v=2.4 cv=ZZ4t8MVA c=1 sm=1 tr=0 ts=69fca0f8 cx=c_pps a=J+5FMm3BkXb42VdG8aMU9w==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=ZswEv4b9r44Tze3PQiwA:9 a=QEXdDO2ut3YA:10 a=Epx66wHExT0cjJnnR-oj:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-07_01,2026-05-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 spamscore=0 priorityscore=1501 bulkscore=0 phishscore=0 clxscore=1015 impostorscore=0 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605070145 On 5/7/2026 6:33 PM, Dmitry Baryshkov wrote: > On the latest A8xx Adreno chips several of the bits in the UBWC-related > registers are now hardwired to 1. Currently the driver doesn't write > them because there is no side-effect. In the preparation for the > refactoring in the next patch, write '1' to those bits anyway. > > Signed-off-by: Dmitry Baryshkov Reviewed-by: Akhil P Oommen -Akhil > --- > drivers/gpu/drm/msm/adreno/a8xx_gpu.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c > index 53def136e0fc..7a6223ddd8cf 100644 > --- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c > +++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c > @@ -288,6 +288,8 @@ static void a8xx_set_ubwc_config(struct msm_gpu *gpu) > switch (ubwc_version) { > case UBWC_6_0: > yuvnotcomptofc = true; > + amsbc = true; > + rgb565_predicator = true; > break; > case UBWC_5_0: > amsbc = true; >