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[91.159.24.186]) by smtp.gmail.com with ESMTPSA id 38308e7fff4ca-37d2412a091sm38320371fa.50.2025.12.02.05.59.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 02 Dec 2025 05:59:12 -0800 (PST) Message-ID: <8ff6ab79-a3d3-48e3-9340-8b91a9ce1b27@linaro.org> Date: Tue, 2 Dec 2025 15:59:03 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 2/3] arm64: dts: qcom: qcs8300: Add CCI definitions To: Vikram Sharma , rfoss@kernel.org, todor.too@gmail.com, bryan.odonoghue@linaro.org, mchehab@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, andersson@kernel.org, konradybcio@kernel.org, hverkuil-cisco@xs4all.nl, cros-qcom-dts-watchers@chromium.org, catalin.marinas@arm.com, will@kernel.org Cc: linux-arm-kernel@lists.infradead.org, nihalkum@qti.qualcomm.com, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Ravi Shankar , Vishal Verma , Suresh Vankadara , Konrad Dybcio References: <20251126081057.4191122-1-quic_vikramsa@quicinc.com> <20251126081057.4191122-3-quic_vikramsa@quicinc.com> From: Vladimir Zapolskiy In-Reply-To: <20251126081057.4191122-3-quic_vikramsa@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 11/26/25 10:10, Vikram Sharma wrote: > From: Nihal Kumar Gupta > > Qualcomm QCS8300 SoC contains three Camera Control Interface (CCI). > Compared to Lemans, the key difference is in SDA/SCL GPIO assignments > and number of CCIs. > > Signed-off-by: Nihal Kumar Gupta > Co-developed-by: Ravi Shankar > Signed-off-by: Ravi Shankar > Co-developed-by: Vishal Verma > Signed-off-by: Vishal Verma > Co-developed-by: Suresh Vankadara > Signed-off-by: Suresh Vankadara > Signed-off-by: Vikram Sharma > Reviewed-by: Vladimir Zapolskiy > Reviewed-by: Bryan O'Donoghue > Reviewed-by: Konrad Dybcio > --- > arch/arm64/boot/dts/qcom/monaco.dtsi | 345 +++++++++++++++++++++++++++ > 1 file changed, 345 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi > index 774255c3f6fc..7c575e1c5e10 100644 > --- a/arch/arm64/boot/dts/qcom/monaco.dtsi > +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi > @@ -4776,6 +4776,117 @@ videocc: clock-controller@abf0000 { > #power-domain-cells = <1>; > }; > > + cci0: cci@ac13000 { > + compatible = "qcom,qcs8300-cci", "qcom,msm8996-cci"; > + reg = <0x0 0x0ac13000 0x0 0x1000>; > + > + interrupts = ; > + > + clocks = <&camcc CAM_CC_CPAS_AHB_CLK>, > + <&camcc CAM_CC_CCI_0_CLK>; > + clock-names = "cpas_ahb", > + "cci"; > + > + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; > + > + pinctrl-0 = <&cci0_0_default &cci0_1_default>; > + pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>; > + pinctrl-names = "default", "sleep"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + > + cci0_i2c0: i2c-bus@0 { > + reg = <0>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + cci0_i2c1: i2c-bus@1 { > + reg = <1>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > + cci1: cci@ac14000 { > + compatible = "qcom,qcs8300-cci", "qcom,msm8996-cci"; > + reg = <0x0 0x0ac14000 0x0 0x1000>; > + > + interrupts = ; > + > + clocks = <&camcc CAM_CC_CPAS_AHB_CLK>, > + <&camcc CAM_CC_CCI_1_CLK>; > + clock-names = "cpas_ahb", > + "cci"; > + > + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; > + > + pinctrl-0 = <&cci1_0_default &cci1_1_default>; > + pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>; > + pinctrl-names = "default", "sleep"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + > + cci1_i2c0: i2c-bus@0 { > + reg = <0>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + cci1_i2c1: i2c-bus@1 { > + reg = <1>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > + cci2: cci@ac15000 { > + compatible = "qcom,qcs8300-cci", "qcom,msm8996-cci"; > + reg = <0x0 0x0ac15000 0x0 0x1000>; > + > + interrupts = ; > + > + clocks = <&camcc CAM_CC_CPAS_AHB_CLK>, > + <&camcc CAM_CC_CCI_2_CLK>; > + clock-names = "cpas_ahb", > + "cci"; > + > + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; > + > + pinctrl-0 = <&cci2_0_default &cci2_1_default>; > + pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>; > + pinctrl-names = "default", "sleep"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + > + cci2_i2c0: i2c-bus@0 { > + reg = <0>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + > + cci2_i2c1: i2c-bus@1 { > + reg = <1>; > + clock-frequency = <1000000>; > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + > camss: isp@ac78000 { > compatible = "qcom,qcs8300-camss"; > > @@ -5071,6 +5182,240 @@ tlmm: pinctrl@f100000 { > #interrupt-cells = <2>; > wakeup-parent = <&pdc>; > > + cam0_avdd_2v8_en_default: cam0-avdd-2v8-en-state { > + pins = "gpio73"; > + function = "gpio"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + cam0_default: cam0-default-state { > + pins = "gpio67"; > + function = "cam_mclk"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + cam1_avdd_2v8_en_default: cam1-avdd-2v8-en-state { > + pins = "gpio74"; > + function = "gpio"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + cam1_default: cam1-default-state { > + pins = "gpio68"; > + function = "cam_mclk"; > + drive-strength = <2>; > + bias-disable; > + }; MCLK pad function declatarions has nothing in common with the CCI, thus it should be split into a separate commit. > + > + cam2_avdd_2v8_en_default: cam2-avdd-2v8-en-state { > + pins = "gpio75"; > + function = "gpio"; > + drive-strength = <2>; > + bias-disable; > + }; All declarations of GPIOs to enable regulators shall be moved to a board specific .dts file. -- Best wishes, Vladimir