Re: [PATCH v3 00/10] Make the 32-bit ARM DMA API work with normal IOMMU DMA default domains (+ Tegra PoC)

[Mikko Perttunen <mperttunen@nvidia.com>]

On Friday, October 30, 2026 7:36 PM Marek Szyprowski wrote:
> On 26.10.2026 10:19, Mikko Perttunen wrote:
> > Depending on the probe ordering, TegraDRM does not currently probe on
> > kernels with CONFIG_ARM_DMA_USE_IOMMU enabled, such as with
> > multi_v7_defconfig. The Tegra SMMU puts several display and 2D/3D
> > clients into one IOMMU group, and the legacy 32-bit ARM DMA API path
> > creates one UNMANAGED domain per device and attaches it with
> > iommu_attach_device(). That only works for one device per group, so
> > every client after the first fails to attach,
> > iommu_device_use_default_domain() rejects the group with -EBUSY, and the
> > driver goes down with it. tegra_defconfig is currently working by virtue
> > of not enabling CONFIG_ARM_DMA_USE_IOMMU.
> >
> > Robin suggested [1] that instead of teaching the legacy path about
> > groups, we should explore modernizing the 32-bit ARM DMA code a bit by
> > making it use domain cookies and have the core code own the domains, as
> > is the case on other architectures. Still, ARM's own DMA code is kept to
> > support existing drivers and APIs that expect it, and because dma-iommu
> > is considered too big and unnecessary for 32-bit ARM.
> >
> > The series is in four parts:
> >
> > - Patches 1-2 are preparation in the IOMMU core:
> >   1. Add iommu_teardown_dma_ops, counterpart to iommu_setup_dma_ops.
> >   2. Add cookie type for ARM's DMA domains.
> > - Patches 3-6 implement the DMA API side on 32-bit ARM:
> >   3. Split up mapping alloc and init (bitmap alloc) code to separate
> >      functions.
> >   4. Implement parallel dma_ops / cookie APIs on ARM side.
> >   5. Avoid domain allocation when IOMMU core does it.
> >   6. Check upper DMA range limit during IOVA allocation.
> > - Patch 7 removes the forced IDENTITY default domain in core IOMMU
> >   code and adds explicit IDENTITY defaults to a few individual IOMMU
> >   drivers.
> > - Patches 8-10 convert Tegra:
> >   8. Fixes device parameter in calls to dma_get_sgtable.
> >   9. Allows deferring translation enable until driver handshake for
> >      selected devices.
> >   10. Switches to DMA default domain for selected Tegra devices.
> >
> > This moves 32-bit ARM devices from the unmanaged IOMMU DMA domain to the
> > core-owned default DMA domain except for mtk_iommu_v1, ipmmu-vmsa,
> > omap-iommu, and msm_iommu. (tegra-smmu also stays on the legacy path
> > until the last patch in the series.) See commit 7 for further
> > information. Existing drivers are intended to continue working without
> > changes.
> >
> > Patches 8-10 are provided for demonstration; we can deal with them 
> > separately if the rest of the series is accepted.
> >
> > Patches 1,2,3,6 are applicable independently.
> > Patches 4,5 depend on the previous patches.
> > Patch 7 requires the prior patches to be in place.
> >
> > Patches 1-7 only touch drivers/iommu/ and arch/arm/mm/ and associated 
> > headers.
> 
> 
> I've tested this patchset on ARM 32bit based Exynos boards and it works
> fine, although I get the following warnings during boot:
> 
> platform 13400000.codec: Adding to iommu group 0
> iommu: Failed to allocate default IOMMU domain of type 0 for group (null) - Falling back to IOMMU_DOMAIN_DMA
> platform 11840000.jpeg-codec: Adding to iommu group 1
> iommu: Failed to allocate default IOMMU domain of type 0 for group (null) - Falling back to IOMMU_DOMAIN_DMA
> 
> This looks like an issue in iommu core, which doesn't expect devices with
> iommu to come up so early.

Excellent, thanks for testing. I'll take a look at the warnings.

Mikko

> 
> 
> LLM proposes the following fix for it:
> 
> diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
> index 197a8f70c6de..612933306684 100644
> --- a/drivers/iommu/iommu.c
> +++ b/drivers/iommu/iommu.c
> @@ -225,10 +225,8 @@ static const char *iommu_domain_type_str(unsigned int t)
>         }
>  }
> 
> -static int __init iommu_subsys_init(void)
> +static void __init iommu_init_def_domain_type(void)
>  {
> -       struct notifier_block *nb;
> -
>         if (!(iommu_cmd_line & IOMMU_CMD_LINE_DMA_API)) {
>                 if (IS_ENABLED(CONFIG_IOMMU_DEFAULT_PASSTHROUGH))
>                         iommu_set_default_passthrough(false);
> @@ -254,6 +252,11 @@ static int __init iommu_subsys_init(void)
>                         iommu_dma_strict ? "strict" : "lazy",
>                         (iommu_cmd_line & IOMMU_CMD_LINE_STRICT) ?
>                                 " (set via kernel command line)" : "");
> +}
> +
> +static int __init iommu_subsys_init(void)
> +{
> +       struct notifier_block *nb;
> 
>         nb = kzalloc_objs(*nb, ARRAY_SIZE(iommu_buses));
>         if (!nb)
> @@ -2939,6 +2942,12 @@ EXPORT_SYMBOL_GPL(report_iommu_fault);
> 
>  static int __init iommu_init(void)
>  {
> +       /*
> +        * Select the default domain type before any IOMMU driver can register
> +        * and create groups, which may happen before subsys_initcall.
> +        */
> +       iommu_init_def_domain_type();
> +
>         iommu_group_kset = kset_create_and_add("iommu_groups",
>                                                NULL, kernel_kobj);
>         BUG_ON(!iommu_group_kset);
> 
> Best regards
> -- 
> Marek Szyprowski, PhD
> Samsung R&D Institute Poland
> 
>