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([2001:818:ea56:d000:94c4:fb0e:28f:2a8d]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-426fb279857sm1628868f8f.20.2025.10.15.10.42.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Oct 2025 10:42:25 -0700 (PDT) Message-ID: <9024f05854dcc3cc59345c0a3de900f57c4730d9.camel@gmail.com> Subject: Re: [PATCH 3/6] spi: add multi_bus_mode field to struct spi_transfer From: Nuno =?ISO-8859-1?Q?S=E1?= To: David Lechner , Mark Brown Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Marcelo Schmitt , Michael Hennerich , Nuno =?ISO-8859-1?Q?S=E1?= , Jonathan Cameron , Andy Shevchenko , Sean Anderson , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org Date: Wed, 15 Oct 2025 17:43:22 +0100 In-Reply-To: References: <20251014-spi-add-multi-bus-support-v1-0-2098c12d6f5f@baylibre.com> <20251014-spi-add-multi-bus-support-v1-3-2098c12d6f5f@baylibre.com> <9269eadc1ea593e5bc8f5cad8061b48220f4d2b2.camel@gmail.com> <409ad505-8846-443e-8d71-baca3c9aef21@sirena.org.uk> <12db0930458ceb596010655736b0a67a0ad0ae53.camel@gmail.com> <8c7bf62a-c5dc-4e4d-8059-8abea15ba94e@sirena.org.uk> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.2 (3.56.2-2.fc42) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 On Wed, 2025-10-15 at 11:15 -0500, David Lechner wrote: > On 10/15/25 10:18 AM, Mark Brown wrote: > > On Wed, Oct 15, 2025 at 03:43:09PM +0100, Nuno S=C3=A1 wrote: > > > On Wed, 2025-10-15 at 13:01 +0100, Mark Brown wrote: > > > > On Wed, Oct 15, 2025 at 11:16:01AM +0100, Nuno S=C3=A1 wrote: > > > > > On Tue, 2025-10-14 at 17:02 -0500, David Lechner wrote: > >=20 > > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 controller=C2=A0=C2= =A0=C2=A0 < data bits <=C2=A0=C2=A0=C2=A0=C2=A0 peripheral > > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 ----------=C2=A0=C2= =A0 ----------------=C2=A0=C2=A0 ---------- > > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 SDI 0=C2=A0=C2=A0=C2=A0 0-0-0-1-0-0-0-1=C2=A0=C2=A0=C2=A0 SDO 0 > > > > > > =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0 SDI 1=C2=A0=C2=A0=C2=A0 1-0-0-0-1-0-0-0=C2=A0=C2=A0=C2=A0 SDO 1 > >=20 > > > > > Out of curiosity, how does this work for devices like AD4030 wher= e the same > > > > > word >=20 > The AD4030 is just one channel, so doesn't do interleaving. But you proba= bly > meant AD4630 when it is wired up with only 1 SDO line. That line has to b= e shared > by both of the simultaneous converters so it alternates between sending o= ne bit > from each word. This patch series doesn't address that case. But this ser= ies will > work for the AD4630 when it has 2 SDO lines wired up. >=20 Hmm I didn't even remembered that one. But what I meant with interleaved wa= s having the same data word spread through multiple SDO lines (one bit per line) whi= ch is what (also) happens with the devices I mentioned. And since you mentioned "...tw= o different data words at the same time, one on each bus...", I raised the qu= estion. So I guess I kind of misused what interleaved typically means (even though = I guess it's not completely off :)) and was thinking more on the parallel concept M= ark spoke about. Anyways, from your reply I see the intent is to also use the stripe mode fo= r this and have some kind of external IP deal with data re-order. I gave a look into t= he ad4630 IP core and indeed there's a data reorder IP block after the offload engine= . - Nuno S=C3=A1 > > > >=20