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[103.229.16.4]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b1ae981c55sm2933013a91.1.2026.11.12.22.26.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Nov 2026 22:26:27 -0800 (PST) Message-ID: <904f7ac1-d488-4700-8839-ae981b04a71b@oss.qualcomm.com> Date: Fri, 13 Nov 2026 14:26:22 +0800 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 0/9] cpufreq: tegra194: add Tegra264 support To: Sumit Gupta , rafael@kernel.org, viresh.kumar@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, treding@nvidia.com, jonathanh@nvidia.com, linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: bbasu@nvidia.com, Zhongqiu Han References: <20261104181521.3003578-1-sumitg@nvidia.com> Content-Language: en-US From: Zhongqiu Han In-Reply-To: <20261104181521.3003578-1-sumitg@nvidia.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=DNgacCNb c=1 sm=1 tr=0 ts=6af6ad97 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=nuhDOHQX5FNHPW3J6Bj6AA==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=c92rfblmAAAA:8 a=Ikd4Dj_1AAAA:8 a=VwQbUJbxAAAA:8 a=I7BNmAFbTgjmseqQuzQA:9 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 a=GvGzcOZaWPEFPQC_NcjD:22 X-Proofpoint-ORIG-GUID: 5Am-3vlRkb36c2N3Jdjhv6Nv0AicVUGh X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTEzMDAyNSBTYWx0ZWRfX5r6KE51SkHCG ygXIILvJj0LfFvxx71Gl0e877G50ElTfd5QAbJ6D8h/lCJjqX/49IP698kMmPfYMyx5MruN6TxH 8CX4YRvuXitI0D6ahKIX9QE6d0wKUmbJqp4AkEXG/b9JRbVOY1erM3+sFbLeCoGIGcNXj8NUKdT NF5m56RIG3pdI+SFOmwmlGguRBz5jwBB1g4OLG4sL0+iEIiVZ+AfYNDmvf2UqAIx6hDW5v6En0q CxB0xTseW57tXd4ANTxHMdEvUUFopjLuGbxU8bBUw/zSkm2wuTiSCf2qkpN3WhSVHgYHHoeoOna jNiO9aee/bFioQxjDLxAp0vlxH+Df4MxqjV7GBu5Ke0Z6D5Q+NFD2Cc2APaudsr0gzfnG1ILLfb i3h+lfNMDcYQKza4YE6U+iZLJogKpzQxVDUNpiXORNBKQ0ktM/FTAtIjo1+DcVLjxuMehqLH6PX jVO+LbfQa08T6T31/sw== X-Proofpoint-Spam-Info: AW1haW4tMjYxMTEzMDAyNSBTYWx0ZWRfX/spN19zcpB1D ZBE1h7lZ11FwN16GPl+geOtbkHJokLCvffoHagiS5lW3+ZdQWBRfgr+SBHmfJX5QChV10hnk4mi lM4tSrzEUtHOE+E8HZbScN4RdfwGzCg= X-Proofpoint-GUID: 5Am-3vlRkb36c2N3Jdjhv6Nv0AicVUGh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-13_02,2026-11-11_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 malwarescore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 impostorscore=0 priorityscore=1501 clxscore=1015 adultscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611130025 Hi Sumit, On 11/5/2026 2:15 AM, Sumit Gupta wrote: > This series adds cpufreq support for Tegra264, which joins the SoCs > already supported by the tegra194-cpufreq driver. > > Tegra264 keeps the existing model, where BPMP provides the NDIV limits. > The driver derives the current frequency from the core clock and > reference counters. > > The main differences are: > - Frequency read: through system registers, as on Tegra194, but from > the 64-bit architected AMU counters. The reference counter ticks at > the system counter rate (CNTFRQ). > > - Frequency request: through MMIO, as on Tegra234. The driver writes > NDIV to a core_freq_req register in the CCPLEX register space. Each > register controls a cluster-clock unit shared by two single-CPU > clusters, so both CPUs form one cpufreq policy. > > The patches fall into four groups: > - Fix (patch 1): read each CPU's MPIDR from a CPU-hotplug callback > instead of at probe. A CPU that is offline at probe then also gets > valid cluster and core IDs. > > - Preparation (patches 2 to 5): cleanups, mostly of the counter code, > to make room for a 64-bit counter and for an MMIO mapping without > ACTMON counters. > > - Improvement (patches 6 and 7): group CPUs by the generic > "performance-domains" property, which cluster-based grouping cannot > express on Tegra264. Device trees without it keep the existing > grouping. > > - Tegra264 support (patches 8 and 9): the driver support, followed by > the device tree changes it relies on. > > Patch 9 depends on "arm64: tegra: Fix address translation on Tegra264" > from Thierry's series [1]. Without it, the ccplex@30000000 node does not > translate to the CCPLEX registers. > I have some inline comments. Please take a look. Sashiko also has some feedback that may be worth checking: https://sashiko.dev/#/patchset/20261104181521.3003578-1-sumitg%40nvidia.com P1 and P8 don't apply on v7.4-rc2 / linux-next due to 4dd10fbbeb9c (devm_kmalloc_obj conversion). Could you rebase? > > Sumit Gupta (9): > cpufreq: tegra194: move MPIDR read to CPU hotplug callback > cpufreq: tegra194: remove duplicate counter sampling loops > cpufreq: tegra194: add tegra_counter_delta helper > cpufreq: tegra194: add per-SoC counter mask > cpufreq: tegra194: split MMIO mapping from ACTMON offset > dt-bindings: arm: nvidia: Document the Tegra264 CCPLEX cluster > cpufreq: tegra194: derive frequency domain from device tree > cpufreq: tegra194: Add support for Tegra264 > arm64: tegra: Add CCPLEX cluster node for Tegra264 > > .../tegra/nvidia,tegra-ccplex-cluster.yaml | 27 +- > arch/arm64/boot/dts/nvidia/tegra264.dtsi | 21 + > drivers/cpufreq/Kconfig.arm | 4 +- > drivers/cpufreq/tegra194-cpufreq.c | 422 +++++++++++++----- > 4 files changed, 357 insertions(+), 117 deletions(-) > > [1] https://lore.kernel.org/linux-tegra/20261030141101.845044-1-thierry.reding@kernel.org/ > -- Thx and BRs, Zhongqiu Han