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([2a01:e0a:106d:1080:8e54:fbaf:8cb6:e9f7]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-486f8ba4a74sm56533335e9.12.2026.03.19.03.33.24 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 19 Mar 2026 03:33:25 -0700 (PDT) Message-ID: <90623d8f-6eee-40e5-ace7-6bd701dd2868@linaro.org> Date: Thu, 19 Mar 2026 11:33:24 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Neil Armstrong Reply-To: Neil Armstrong Subject: Re: [PATCH v2 3/3] drm/msm/dpu: fix video mode DSC INTF timing width for non 8 bit panels To: Alexander Koskovich Cc: Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org References: <20260318-dsi-rgb101010-support-v2-0-698b7612eaeb@pm.me> <20260318-dsi-rgb101010-support-v2-3-698b7612eaeb@pm.me> <_varXMigTiaLa1CVxsqWY0wJNnR8xZGw5lAS8MmyxrVAjHPK1Mu-H-heiIMxB9SdcJoEhjUDUtUo8dZvTi_GsQwYKsuGnc1tsFlSDqoKfA0=@pm.me> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <_varXMigTiaLa1CVxsqWY0wJNnR8xZGw5lAS8MmyxrVAjHPK1Mu-H-heiIMxB9SdcJoEhjUDUtUo8dZvTi_GsQwYKsuGnc1tsFlSDqoKfA0=@pm.me> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 3/19/26 09:48, Alexander Koskovich wrote: > On Thursday, March 19th, 2026 at 4:35 AM, Neil Armstrong wrote: > >> On 3/19/26 05:00, Alexander Koskovich wrote: >>> Using bits_per_component * 3 as the divisor for the compressed INTF >>> timing width produces constant FIFO errors for panels such as the BOE >>> BF068MWM-TD0 which is a 10 bit panel. >>> >>> The downstream driver calculates the compressed timing width by >>> dividing the total compressed bytes per line by 3 which does not depend >>> on bits_per_component. Switch the divisor to 24 to match downstream. >>> >>> Signed-off-by: Alexander Koskovich >>> --- >>> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 12 +++++++----- >>> 1 file changed, 7 insertions(+), 5 deletions(-) >>> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c >>> index 0ba777bda253..9b046a0e77aa 100644 >>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c >>> @@ -122,19 +122,21 @@ static void drm_mode_to_intf_timing_params( >>> } >>> >>> /* >>> - * for DSI, if compression is enabled, then divide the horizonal active >>> - * timing parameters by compression ratio. bits of 3 components(R/G/B) >>> - * is compressed into bits of 1 pixel. >>> + * For DSI, if DSC is enabled, use a fixed divisor of 24 rather than >>> + * bits_per_component * 3 when calculating the compressed timing width. >>> + * >>> + * This matches the downstream driver and is required for panels with >>> + * bits_per_component != 8. >>> */ >>> if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) { >>> struct drm_dsc_config *dsc = >>> dpu_encoder_get_dsc_config(phys_enc->parent); >>> + >>> /* >>> * TODO: replace drm_dsc_get_bpp_int with logic to handle >>> * fractional part if there is fraction >>> */ >>> - timing->width = timing->width * drm_dsc_get_bpp_int(dsc) / >>> - (dsc->bits_per_component * 3); >>> + timing->width = timing->width * drm_dsc_get_bpp_int(dsc) / 24; >> >> >> >> @bits_per_component: Bits per component to code (8/10/12) <= how the DSC pixels are encoded in the stream >> @bits_per_pixel: Target bits per pixel with 4 fractional bits, bits_per_pixel << 4 <= the target display pixels >> >> - bits_per_component is the transport width >> - bits_per_pixel is the display width >> - 3 is the DSC compression ratio >> >> So for a RGB101010 DSC display bits_per_pixel should be 10 << 4 >> >> But here you say bits_per_component should be 8 ? can you share the downstream config of your panel ? > > This is what is defined downstream for this panel, they're using 8: > https://github.com/NothingOSS/android_kernel_msm-6.1_nothing_sm7635/blob/sm7635/b/mr/vendor/qcom/proprietary/display-devicetree/display/dsi-panel-rm69220-dsc-fhd-plus-120hz-vid-boe.dtsi > >> >> Are you sure about the bits_per_component & bits_per_pixel values you set in the dsc parameters ? > > I'm pretty sure they're correct, here's the panel driver I have atm: > https://github.com/AKoskovich/linux/blob/asteroids-6.19.y/drivers/gpu/drm/panel/panel-boe-bf068mwm-td0.c So I looked at downstream, and bit-per-component is not used at all for the width calculation. Here's the full downstream calculation with your panel: intf_width = mode->timing.h_active; => 1080 slice_per_pkt = dsc_info->slice_per_pkt; => 2 slice_per_intf = DIV_ROUND_UP(intf_width, dsc_info->config.slice_width); => 1080/540 = 2 if (slice_per_pkt > slice_per_intf) slice_per_pkt = 1; bpp = DSC_BPP(dsc_info->config); => 8 bytes_in_slice = DIV_ROUND_UP(dsc_info->config.slice_width * bpp, 8); => 540 * 8 / 8 = 540 dsc_info->bytes_per_pkt = bytes_in_slice * slice_per_pkt; => 540 * 2 = 1080 dsc_info->pkt_per_line = slice_per_intf / slice_per_pkt; => 2 / 2 = 1 ... phys->dce_bytes_per_line = comp_info->dsc_info.bytes_per_pkt * comp_info->dsc_info.pkt_per_line; => 1080 * 1 = 1080 ... if (p->compression_en) { if (p->wide_bus_en) data_width = DIV_ROUND_UP(p->dce_bytes_per_line, 6); => 1080 / 6 = 180 else data_width = DIV_ROUND_UP(p->dce_bytes_per_line, 3); => 1080 / 3 = 360 } So you're right, it should be a fixed (8 * 3) division, and a (8 * 6) in case of widebus, but DSI widebus is not yet handled. Neil > >> >> Neil >> >> >>> timing->xres = timing->width; >>> } >>> } >>> >> >> > > Thanks, > Alex