From: Gong Shuai <gsh517025@gmail.com>
To: fangyu.yu@linux.alibaba.com
Cc: guoren@kernel.org, iommu@lists.linux.dev,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
kvm-riscv@lists.infradead.org, tomasz.jeznach@linux.dev,
joro@8bytes.org, will@kernel.org, robin.murphy@arm.com,
pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu,
alex@ghiti.fr, baolu.lu@linux.intel.com, jroedel@suse.de,
zong.li@sifive.com, andrew.jones@oss.qualcomm.com,
anup@brainfault.org, jgg@nvidia.com, jgg@ziepe.ca,
kevin.tian@intel.com, atish.patra@linux.dev, skhawaja@google.com,
vasant.hegde@amd.com, joerg.roedel@amd.com,
gong.shuai@sanechips.com.cn
Subject: Re: [RFC PATCH v4 08/10] iommu/riscv: Pre-enable GADE for second-stage domains
Date: Sat, 19 Sep 2026 00:18:34 +0800 [thread overview]
Message-ID: <90826872-1374-49e4-832d-555abf8e8369@gmail.com> (raw)
In-Reply-To: <20260915032828.11250-9-fangyu.yu@linux.alibaba.com>
Hi Fangyu,
On 9/15/2026 11:28 AM, fangyu.yu@linux.alibaba.com wrote:
> From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
>
> Pre-enable RISCV_IOMMU_DC_TC_GADE in the device context when
> attaching a second-stage domain, if the IOMMU supports AMO_HWAD.
>
> Software pre-populates second-stage page tables with D set, so
> enabling GADE by default does not change normal behavior. When
> dirty tracking is enabled, iommufd clears the pre-set D bits and
> GADE becomes necessary for hardware to update the dirty bit on
> write access.
>
> This avoids toggling GADE dynamically and keeps device context
> setup consistent with second-stage domain attachment.
>
> Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
> ---
> drivers/iommu/riscv/iommu.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/iommu/riscv/iommu.c b/drivers/iommu/riscv/iommu.c
> index 16779877351b..f01fd4e2f840 100644
> --- a/drivers/iommu/riscv/iommu.c
> +++ b/drivers/iommu/riscv/iommu.c
> @@ -1330,6 +1330,8 @@ static int riscv_iommu_attach_paging_domain(struct iommu_domain *iommu_domain,
> FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_MODE, pt_info.iohgatp_mode) |
> FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_GSCID, domain->gscid) |
> FIELD_PREP(RISCV_IOMMU_DC_IOHGATP_PPN, pt_info.ppn);
> + if (iommu->caps & RISCV_IOMMU_CAPABILITIES_AMO_HWAD)
> + dc.tc |= RISCV_IOMMU_DC_TC_GADE;
I might be missing something, but I don't see how the GADE bit set
here reaches the hardware IOMMU DC. In riscv_iommu_iodir_update()
(in patch 04/10), it looks like only the V bit is taken:
tc = READ_ONCE(dc->tc);
tc |= new_dc->ta & RISCV_IOMMU_DC_TC_V;
...
WRITE_ONCE(dc->tc, tc);
I saw that you mentioned you tested it on QEMU. As far as I know,
mainline QEMU has not yet declared the AMO_HWAD capability. Could
you clarify whether you used a modified QEMU for this test?
Thanks,
Shuai
> } else {
> if (!riscv_iommu_fsc_supported(iommu, pt_info.fsc_iosatp_mode))
> return -ENODEV;
next prev parent reply other threads:[~2026-09-18 16:18 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-15 3:28 [RFC PATCH v4 00/10] iommu/riscv: Add hardware dirty tracking " fangyu.yu
2026-09-15 3:28 ` [RFC PATCH v4 01/10] iommupt: Add RISC-V Second-stage (iohgatp) page table support fangyu.yu
2026-09-15 3:28 ` [RFC PATCH v4 02/10] iommupt: Add RISC-V dirty tracking PTE ops fangyu.yu
2026-09-15 3:28 ` [RFC PATCH v4 03/10] iommu/riscv: report iommu capabilities fangyu.yu
2026-09-18 3:39 ` Nutty.Liu
2026-09-15 3:28 ` [RFC PATCH v4 04/10] iommu/riscv: use data structure instead of individual values fangyu.yu
2026-09-18 3:42 ` Nutty.Liu
2026-09-18 16:08 ` Gong Shuai
2026-09-15 3:28 ` [RFC PATCH v4 05/10] iommu/riscv: support GSCID and GVMA invalidation command fangyu.yu
2026-09-18 4:03 ` Nutty.Liu
2026-09-15 3:28 ` [RFC PATCH v4 06/10] RISC-V: KVM: Enable KVM_VFIO interfaces on RISC-V arch fangyu.yu
2026-09-18 4:03 ` Nutty.Liu
2026-09-15 3:28 ` [RFC PATCH v4 07/10] iommu/riscv: Add domain_alloc_paging_flags for second-stage domain fangyu.yu
2026-09-15 3:28 ` [RFC PATCH v4 08/10] iommu/riscv: Pre-enable GADE for second-stage domains fangyu.yu
2026-09-18 16:18 ` Gong Shuai [this message]
2026-09-15 3:28 ` [RFC PATCH v4 09/10] iommu/riscv: Add dirty tracking support " fangyu.yu
2026-09-17 1:40 ` [RFC PATCH v4 00/10] iommu/riscv: Add hardware dirty tracking " Gong Shuai
2026-09-17 2:02 ` fangyu.yu
2026-09-17 2:54 ` [RFC PATCH v4 10/10] iommu/riscv: Add IOTINVAL.GVMA after updating DDT/PDT entries fangyu.yu
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